74AUP1G74DC,125 NXP Semiconductors, 74AUP1G74DC,125 Datasheet - Page 15

• Manufacturer Part Number: 74AUP1G74DC,125
• Description: IC F-F D-TYPE POS EDGE 8VSSOP
• Manufacturer: NXP Semiconductors
• Series: 74AUPr
• Type: D-Typer

Specifications of 74AUP1G74DC,125

• Output Type: Differential
• Package / Case: US8, 8-VSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 550MHz
• Delay Time - Propagation: 2.2ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: AUP
• Logic Type: CMOS
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 22.5 ns
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 0.8 V
• Technology: CMOS
• Number Of Bits: 1
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AUP1G74DC-G; 74AUP1G74DC-G; 935280717125

NXP Semiconductors
12. Waveforms
Table 10.
74AUP1G74
Product data sheet
Supply voltage
V
0.8 V to 3.6 V
Fig 8.
CC
Measurement points are given in
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
The clock input (CP) to output (Q, Q) propagation delays, the data input (D) to clock input (CP) set-up and
hold times and the clock input (CP) pulse width and maximum frequency
OL
Measurement points
and V
OH
are typical output voltage levels that occur with the output load.
CP input
Q output
Q output
D input
Output
V
0.5 × V
M
GND
GND
V
V
V
V
CC
OH
OH
OL
OL
V
V
I
I
Table
All information provided in this document is subject to legal disclaimers.
Low-power D-type flip-flop with set and reset; positive-edge trigger
10.
V
M
t
su
Rev. 5 — 26 July 2010
Input
V
0.5 × V
M
t
V
h
M
CC
V
V
M
M
t
t
PHL
PLH
1/f
max
t
W
t
su
V
V
I
CC
t
h
001aae365
t
t
PLH
PHL
74AUP1G74
t
≤ 3.0 ns
r
= t
© NXP B.V. 2010. All rights reserved.
f
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