74AUP1G74DC,125 NXP Semiconductors, 74AUP1G74DC,125 Datasheet - Page 4

• Manufacturer Part Number: 74AUP1G74DC,125
• Description: IC F-F D-TYPE POS EDGE 8VSSOP
• Manufacturer: NXP Semiconductors
• Series: 74AUPr
• Type: D-Typer

Specifications of 74AUP1G74DC,125

• Output Type: Differential
• Package / Case: US8, 8-VSSOP
• Function: Set(Preset) and Reset
• Number Of Elements: 1
• Number Of Bits Per Element: 1
• Frequency - Clock: 550MHz
• Delay Time - Propagation: 2.2ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 0.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: AUP
• Logic Type: CMOS
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 22.5 ns
• High Level Output Current: - 4 mA
• Low Level Output Current: 4 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 0.8 V
• Technology: CMOS
• Number Of Bits: 1
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (min): 0.8V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 125C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AUP1G74DC-G; 74AUP1G74DC-G; 935280717125

NXP Semiconductors
Table 3.
7. Functional description
Table 4.
[1]
74AUP1G74
Product data sheet
Symbol
CP
D
Q
GND
Q
RD
SD
V
Input
SD
L
H
L
Fig 6.
CC
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Pin configuration SOT996-2
GND
Pin description
Function table for asynchronous operation
CP
Q
D
Pin
SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
1
2
3
4
5
6
7
8
1
2
3
4
6.2 Pin description
RD
H
L
L
Transparent top view
74AUP1G74
001aai217
CP
X
X
X
All information provided in this document is subject to legal disclaimers.
8
7
6
5
Low-power D-type flip-flop with set and reset; positive-edge trigger
V
SD
RD
Q
CC
Rev. 5 — 26 July 2010
4
SOT902-1
7
6
5
3
2
1
8
[1]
D
X
X
X
Fig 7.
Pin configuration SOT902-1
terminal 1
index area
Description
clock input
data input
complement output
ground (0 V)
true output
asynchronous reset input (active LOW)
asynchronous set input (active LOW)
supply voltage
RD
SD
Q
Output
Q
H
L
H
1
2
3
Transparent top view
74AUP1G74
74AUP1G74
© NXP B.V. 2010. All rights reserved.
Q
L
H
H
7
6
5
001aae324
CP
D
Q
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