74AUP1G74DC,125 NXP Semiconductors, 74AUP1G74DC,125 Datasheet - Page 22
![IC F-F D-TYPE POS EDGE 8VSSOP](/photos/6/94/69485/8-vssop_sot765-1_sml.jpg)
74AUP1G74DC,125
Manufacturer Part Number
74AUP1G74DC,125
Description
IC F-F D-TYPE POS EDGE 8VSSOP
Manufacturer
NXP Semiconductors
Series
74AUPr
Type
D-Typer
Datasheet
1.74AUP1G74GM125.pdf
(28 pages)
Specifications of 74AUP1G74DC,125
Output Type
Differential
Package / Case
US8, 8-VSSOP
Function
Set(Preset) and Reset
Number Of Elements
1
Number Of Bits Per Element
1
Frequency - Clock
550MHz
Delay Time - Propagation
2.2ns
Trigger Type
Positive Edge
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
AUP
Logic Type
CMOS
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
22.5 ns
High Level Output Current
- 4 mA
Low Level Output Current
4 mA
Supply Voltage (max)
3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
0.8 V
Technology
CMOS
Number Of Bits
1
Number Of Elements
1
Clock-edge Trigger Type
Positive-Edge
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Supply Voltage (min)
0.8V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AUP1G74DC-G
74AUP1G74DC-G
935280717125
74AUP1G74DC-G
935280717125
NXP Semiconductors
Fig 15. Package outline SOT902-1 (XQFN8U)
74AUP1G74
Product data sheet
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
SOT902-1
VERSION
OUTLINE
not for soldering
metal area
max
0.5
A
terminal 1
index area
terminal 1
index area
0.05
0.00
A
L
1
1
3
2
1
0.25
0.15
b
IEC
- - -
L
1.65
1.55
D
e
1.65
1.55
E
4
8
D
0.55
MO-255
JEDEC
e
0
All information provided in this document is subject to legal disclaimers.
e
Low-power D-type flip-flop with set and reset; positive-edge trigger
REFERENCES
0.5
e
1
0.35
0.25
Rev. 5 — 26 July 2010
L
5
6
7
B
b
0.15
0.05
JEITA
L
- - -
1
e
e
A
E
scale
1
1
1
∅ v
∅ w
0.1
v
M
M
C
C
0.05
w
A
B
0.05
y
A
2 mm
0.05
y
A
y
1
1
1
C
PROJECTION
EUROPEAN
detail X
74AUP1G74
X
C
© NXP B.V. 2010. All rights reserved.
y
ISSUE DATE
05-11-25
07-11-14
SOT902-1
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