rs5c62 RICOH Co.,Ltd., rs5c62 Datasheet - Page 18

• Manufacturer Part Number: rs5c62
• Description: Real-time Clock
• Manufacturer: RICOH Co.,Ltd.

14
RP/RF/RS5C62
2.9 Timer Clock Selection Register (BANK1 at “Ch”)
T1 : Maximum time during which timer output is disabled after timer resetting.
T2 : Time between timer output and cycle setting during timer resetting (upon setting the TM
T3 : Timer output cycle without timer reset.
*
*
TM
TM
TM
1) Only the TM
2) The TM
D3
0
1
1
1
1
1
1
1
1
(Timer reset occurs upon setting the TMR bit to “1” in the control register 1.)
(Timer output occurs upon driving low the TMOUT pin output.)
or timer resetting, or transition of the CE pin input from its low to high levels.
3
3
3
3
to TM
TM
TM
D2
*
0
0
0
0
0
1
1
1
1
3
2
bit is intended for read operation. The D0 bit is always read as “TMFG”. The D2 and D1 bits are always read as “0”.
2
0
bits are used to set cycles for the counters as shown in the table below.
TM
D1
TM
0
*
0
0
1
1
0
0
1
1
1
1
TMFG
TM
D0
TM
*
0
1
0
1
0
1
0
1
0
0
Timer counter cycle setting bit (TM
Timer output indication bit (TMFG) *
(For write operation)
(For read operation)
(TMOUT pin output turned off)
Timer output disabled
(Watchdog timer cycle)
70.3ms
35.1ms
17.5ms
8.78ms
4.39ms
562ms
281ms
140ms
T1
*
1
(Output time after timer resetting) (Free-running timer cycle)
(TMOUT pin output turned off)
Timer output disabled
70.3 to 78.2ms
35.1 to 39.1ms
17.5 to 19.6ms
8.78 to 9.77ms
4.39 to 4.89ms
562 to 626ms
281 to 313ms
140 to 157ms
3
to TM
T2
3
0
) *
2
(TMOUT pin output turned off)
Timer output disabled
3
bit to “0” ),
312.5ms
156.3ms
78.13ms
39.06ms
19.53ms
9.766ms
4.883ms
625ms
T3