rs5c62 RICOH Co.,Ltd., rs5c62 Datasheet - Page 21

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rs5c62

Manufacturer Part Number
rs5c62
Description
Real-time Clock
Manufacturer
RICOH Co.,Ltd.
Datasheet

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USAGE
1. Reading and Writing Operations
1.1 Reading Operation
performing the process of addressing through the A3 to A0 pin inputs, then [3] driving low the CS pin, [4] causing
the RD pin to transition from its high to low levels, and thereby [5] causing the D3 to D0 pins to output read data.
The reading timing is shown in the chart below.
D3 to D0
A3 to A0
*
*
*
The requirements for reading data from the internal registers and counters are: [1] holding the CE pin high, [2]
1) The CS and RD pin inputs are interchangeable. The diagonally shaded sections marked in the above timing chart may be set to both high and low
2) “
3) “
WR
CE
RD
CS
levels. (Consequently, the CS and RD pin inputs may be caused to transition from their high to low levels before the process of addressing.)
are driven low.
is driven high.
t
t
AS
AH
(RD)” indicates the time required to perform the process of addressing before the start of read operation at which both the RD and CS pin inputs
(RD)”indicates the time required to maintain the result of addressing after the completion of read operation at which either the RD or CS pin input
RD
CS
(Read Data)
D0 to D3
A0 to A3
or
RD
CS
CE
[1]
t
CES
Address
Reading operation
Writing operation
Data bus
[3]
[2]
[4]
t
t
RR
AS(RD)
[5]
Upon driving high the CE pin, the interfacing input/out-
put pins are enabled, establishing equivalence in logic
between the RD and CS pin inputs during read opera-
tion and between the WR and CS pin inputs during
write operation. Upon driving low the CE pin, the inter-
facing input/output pins are disabled, preventing occur-
rence of invalid leak current due to their floating. The
CE pin must always be driven either high or low and
must never be left floating.
t
Valid
AH(RD)
t
RZ
t
CEH
RP/RF/RS5C62
17

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