rs5c62 RICOH Co.,Ltd., rs5c62 Datasheet - Page 27

• Manufacturer Part Number: rs5c62
• Description: Real-time Clock
• Manufacturer: RICOH Co.,Ltd.

5.2 Cyclic Interrupt
rupt cycle, the INTR pin is driven low (turned on) to output an request for a cyclic interrupt. A cyclic interrupt can
be output from the INTR pin in the pulse mode and the level mode. In the level mode in particular, a cyclic interrupt
can be disabled by setting the CTFG bit to “0” in the control register 2.
• Pulse mode
• Level mode
6. Timer
The timer counter can be reset conditional on restart by setting the TMR bit to “1” in the control register 1. (It can
act as a watchdog timer.)
Cyclic Interrupt
Interrupt cycle selection register
CTFG bit
(The CT
(The CTFG bit is not intended for write
operation.)
(The CT
(The CTFG bit is intended for setting to
“0” only.)
*
*
*
*
*
*
*
A desired interrupt cycle can be preset in the bits in the interrupt cycle selection register. With the preset inter-
Available interrupt cycles: 6 types (0.488ms, 0.977ms, 7.813ms, 62.5ms, 1s, and 60s)
Available output modes: 2 types (pulse mode and level mode)
Upon lapse of time preset in the timer clock selection register, cyclic pulses are output from the TMOUT pin.
1)
2) The above figure assumes that a cyclic interrupt occurs in the absence of an alarm interrupt.
3) The CTFG bit has an inverse logic from that of the INTR pin output.
1) The timer is stopped upon driving low the CE pin input, but restarted upon driving high the CE pin input.
2) Timer output is disabled upon resetting the TM
3) The T3 to T1 bits are described in “2. 9 Timer Clock Selection Register”.
4) Timer output is turned off upon setting the TMR bit to “1” in the control register 1 during timer output.
A preset interrupt cycle can be canceled by setting the bits to “0” in the interrupt cycle selection register.
3
3
bit is set to “0”.)
bit is set to “1”.)
TMOUT
TMFG
Setting the TMR bit to “1”
(See “2.5 Interrupt Cycle Selection Register”)
(See “2.2 Control Register 2”)
MAX.T
3
bit to “0” when the stop of oscillation is detected.
Setting the TMR bit to “1”
1
CTFG
CTFG
INTR
INTR
T
2
Interrupt
Preset interrupt cycle
0.244ms
T
3
(Interrupt)
Setting the CTFG bit to “0”
RP/RF/RS5C62
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