rs5c62 RICOH Co.,Ltd., rs5c62 Datasheet - Page 35

• Manufacturer Part Number: rs5c62
• Description: Real-time Clock
• Manufacturer: RICOH Co.,Ltd.

11.2 Writing to or Reading from Time and Calendar Counters
writing to the time and calendar counters requires stopping time count operation (by setting that the WTEN bit to
“0” in the control register 1) and confirming the absence of a carry (by checking that the BSY bit to “0” in the con-
trol register 2). On the other hand, reading from the time and calendar counters may be performed by stopping
time count operation, generating a cyclic interrupt, or dual reading.
11.2-1 Writing to or Reading from Time and Calendar Counters by Stopping Time Count Operation
Writing to the time and calendar counters must be performed in the absence of a carry. In particular, correct
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(by Setting WTEN and checking BSY bits)
Write to or read from time
and calendar counters
Set 12- or 24-hour
WTEN
WTEN
BANK
time scale
BSY=0?
YES
0
0
1
*
*
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NO
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1
2
3
4
6
Wait
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1) Set the 12- or 24-hour time scale once before writing to the time and cal-
3) When the BSY bit is set to “1” in the control register 2, continue reading
4) Writing to the 1-year or 10-year counter automatically enables leap year
5) When reading from the time and calendar counters, ensure that this route
6) Restart time count operation. (The WTEN bit will automatically be set to
7)
2)
endar counters (at the time of initialization after power-on from 0V).
Set the WTEN bit to “0” in the control register 1 to stop the second and
from the time and calendar counters until it is set to “0” or wait for 122.1
µs or more. When the BSY bit is set to “0”, it is kept at “0” until the
WTEN bit is set to “1” again in the control register 1.
indication. To disable leap year indication, write “4h” (set the LYE bit to
“1” ) in the leap year indication register after setting the time and calen-
dar counters. Note that leap year indication is continued without correc-
tion until the year 2099.
lasts within 1 second. If this route lasts within 1 second, the 1-second
digit is incremented by 1 to correct a 1-second carry occurring during
read operation upon setting the WTEN bit to “1” again in the control reg-
ister 1. Note that the 1-second digit is also incremented by 1 to correct
more than one 1-second carry while the WTEN bit is kept at “0”, resulting
in a clock delay.
“1” in the control register 1 upon driving low the CE pin.)
BSY bit in the control register 2 by disabling a carry (by setting the
WTEN bit to “0” ).
higher-order digits.
When writing to the time and calendar counters, be sure to check the
RP/RF/RS5C62
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