74LVT16374ADL,112 NXP Semiconductors, 74LVT16374ADL,112 Datasheet
74LVT16374ADL,112
Specifications of 74LVT16374ADL,112
74LVT16374ADL
935184410112
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74LVT16374ADL,112 Summary of contents
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V 16-bit edge-triggered D-type flip-flop; 3-state Rev. 07 — 22 March 2010 1. General description The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for V operation at 3 This device is a 16-bit edge-triggered ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +85 °C 74LVT16374ADL −40 °C to +85 °C 74LVT16374ADGG 74LVTH16374ADGG −40 °C to +85 °C 74LVT16374AEV −40 °C to +85 °C 74LVTH16374ABQ 4. Functional diagram 1D0 1D1 1D2 1D3 48 1CP ...
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... NXP Semiconductors nD0 nD1 nCP nOE nQ0 Fig 3. Logic diagram 5. Pinning information 5.1 Pinning 74LVT16374A 74LVTH16374A 1OE 1 1Q0 2 3 1Q1 4 GND 1Q2 5 1Q3 1Q4 9 1Q5 GND 10 1Q6 11 1Q7 12 13 2Q0 14 2Q1 GND 15 2Q2 16 2Q3 2Q4 2Q5 20 GND 21 2Q6 22 23 2Q7 24 2OE Fig 4 ...
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... NXP Semiconductors terminal 1 index area (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 6. Pin configuration SOT1134-1 (HXQFN60U) 74LVT_LVTH16374A_7 Product data sheet 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state D1 A32 ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin SOT370-1 and SOT362-1 1OE, 2OE 1, 24 1CP, 2CP 48, 25 1Q0 to 1Q7 11, 12 2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 GND 4, 10, 15, 21, 28, 34, 39 18, 31 1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 2D0 to 2D7 ...
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... NXP Semiconductors 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O I input clamping current IK I output clamping current OK I output current ...
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... NXP Semiconductors 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V input clamping voltage IK V HIGH-level output voltage LOW-level output voltage power-up LOW-level OL(pu) output voltage I input leakage current ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ΔI additional supply current CC C input capacitance I C output capacitance O [1] Typical values are measured at V [2] For valid test results, data must not be loaded into the flips-flops (or latches) after applying power. ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter t set-up time su t hold time h t pulse width W [1] All typical values are 3.3 V and the same as t and t su su(H) su(L) [ the same as t and t ...
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... NXP Semiconductors nOE input nYn output nYn output Measurements points are given in V and V are typical voltage output levels that occur with the output load Fig 8. Enable and disable times nCP input nDn input nQn output Measurement points are given in V and V are typical voltage output levels that occur with the output load ...
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... NXP Semiconductors Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 10. Test circuit for measuring switching times Table 9. Test data Input ...
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... NXP Semiconductors 12. Package outline SSOP48: plastic shrink small outline package; 48 leads; body width 7 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.4 2.35 mm 2.8 0.25 0.2 2.20 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE ...
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... NXP Semiconductors TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6 pin 1 index 1 DIMENSIONS (mm are the original dimensions). A UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.85 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4 0.65 mm ball A1 index area ball A1 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max. 0.3 0.7 0. 0.2 0.6 0.35 OUTLINE VERSION IEC SOT702-1 Fig 13. Package outline SOT702-1 (VFBGA56) ...
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... NXP Semiconductors HXQFN60U: plastic thermal enhanced extremely thin quad flat package; no leads; 60 terminals; UTLP based; body 0.5 mm terminal 1 index area A10 terminal 1 index area D1 Dimensions Unit max 0.50 0.05 0.35 4.1 mm nom 0.48 0.02 0.30 4.0 min 0.46 0.00 0.25 3.9 ...
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... Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added type numbers 74LVTH16374ADGG (TSSOP48) and 74LVTH16374ABQ (HUQFN60U) ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74LVT_LVTH16374A_7 Product data sheet 74LVT16374A; 74LVTH16374A 3.3 V 16-bit edge-triggered D-type flip-flop; 3-state http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 07 — 22 March 2010 © ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 Abbreviations ...