74LVT16374ADL,112 NXP Semiconductors, 74LVT16374ADL,112 Datasheet - Page 5

• Manufacturer Part Number: 74LVT16374ADL,112
• Description: IC 16BIT EDG-TRIG D FF 48SSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr
• Type: D-Type Busr

Specifications of 74LVT16374ADL,112

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 2
• Number Of Bits Per Element: 8
• Frequency - Clock: 150MHz
• Delay Time - Propagation: 3ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Logic Family: LVT
• Technology: BiCMOS
• Number Of Bits: 16
• Number Of Elements: 2
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Operating Supply Voltage (typ): 3.3V
• Package Type: SSOP
• Propagation Delay Time: 6ns
• Low Level Output Current: 64mA
• High Level Output Current: -32mA
• Frequency (max): 150MHz
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74LVT16374ADL; 74LVT16374ADL; 935184410112

NXP Semiconductors
Table 2.
6. Functional description
Table 3.
[1]
74LVT_LVTH16374A_7
Product data sheet
Symbol
1OE, 2OE
1CP, 2CP
1Q0 to 1Q7
2Q0 to 2Q7
GND
V
1D0 to 1D7
2D0 to 2D7
n.c.
Operating mode
Load and read register
Hold
Disable outputs
CC
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition.
Pin description
Function table
Pin
SOT370-1 and
SOT362-1
1, 24
48, 25
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20,
22, 23
4, 10, 15, 21, 28, 34, 39,
45
7, 18, 31, 42
47, 46, 44, 43, 41, 40,
38, 37
36, 35, 33, 32, 30, 29,
27, 26
-
5.2 Pin description
[1]
Input
nOE
L
L
L
H
H
SOT702-1
A1, K1
A6, K6
B2, B1, C2, C1, D2,
D1, E2, E1
F1, F2, G1, G2, H1,
H2, J1, J2
B3, D3, G3, J3, J4,
G4, D4, B4
C3, H3, H4, C4
B5, B6, C5, C6, D5,
D6, E5, E6
F6, F5, G6, G5, H6,
H5, J6, J5
A2, A3, A4, A5,
K2, K3, K4, K5
All information provided in this document is subject to legal disclaimers.
nCP
↑
↑
NC
NC
↑
Rev. 07 — 22 March 2010
74LVT16374A; 74LVTH16374A
nDn
l
h
X
X
nDn
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
SOT1134-1
A30, A13
A29, A14
B20, A31, D5, D1, A2,
B2, B3, A5
A6, B5, B6, A9, D2,
D6, A12, B8
A32, A3, A8, A11, A16,
A19, A24, A27
A1, A10, A17, A26
B18, A28, D8, D4,
A25, B16, B15, A22
A21, B13, B12, A18,
D3, D7, A15, B10
A4, A7, A20, A23, B1,
B4, B7, B9, B11, B14,
B17, B19
Internal register
L
H
NC
NC
nDn
Description
output enable input (active LOW)
clock input
data output
data output
ground (0 V)
supply voltage
data input
data input
not connected
Output
nQ0 to nQ7
L
H
NC
Z
Z
© NXP B.V. 2010. All rights reserved.
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