st7fmc2s7t6 STMicroelectronics, st7fmc2s7t6 Datasheet - Page 207

• Manufacturer Part Number: st7fmc2s7t6
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, Five Timers, Spi, Linsci
• Manufacturer: STMicroelectronics

MOTOR CONTROLLER (Cont’d)
A
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = AN[7:0]: A Weight Value.
These bits contain the A
tiplier. In autoswitched mode the MCOMP register
is automatically loaded with:
when a Z event occurs.
(*) depending on the DCB bit in the MCRA regis-
ter.
PRESCALER & SAMPLING REGISTER
(MPRSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:4 = SA[3:0]: Sampling Ratio.
These bits contain the sampling ratio value for cur-
rent mode. Refer to Table 47, “Sampling Frequen-
cy Selection,” on page 188.
Bits 3:0 = ST[3:0]: Step Ratio.
These bits contain the step ratio value. It acts as a
prescaler for the MTIM timer and is auto incre-
mented/decremented with each R+ or R- event.
Refer to Table 40, “Step Frequency/Period Range
(4MHz),” on page 178
Accessing MTIM Timer-Related Registers,” on
page 178.
Z
AN7
SA3
N
n
7
7
WEIGHT REGISTER (MWGHT)
x MWGHT
256(d)
AN6
SA2
6
6
AN5
SA1
5
5
or
Z
AN4
SA0
N
4
4
-1
N
x MWGHT
and Table 41, “Modes of
256(d)
weight value for the mul-
AN3
ST3
3
3
AN2
ST2
2
2
(*)
AN1
ST1
1
1
AN0
ST0
0
0
INTERRUPT MASK REGISTER (MIMR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = PUM: PWM Update Mask bit.
0: PWM Update interrupt disabled
1: PWM Update interrupt enabled
Bit 6 = SEM: Speed Error Mask bit.
0: Speed Error interrupt disabled
1: Speed Error interrupt enabled
Bit 5 = RIM: Ratio update Interrupt Mask bit.
0: Ratio update interrupts (R+ and R-) disabled
1: Ratio update interrupts (R+ and R-) enabled
Bit 4 = CLIM: Current Limitation Interrupt Mask bit.
0: Current Limitation interrupt disabled
1: Current Limitation interrupt enabled
This interrupt is available only in Voltage Mode
(VOC1 bit=0 in MCRA register) and occurs when
the Motor current feedback reaches the external
current limitation value.
Bit 3 = EIM: Emergency stop Interrupt Mask bit.
0: Emergency stop interrupt disabled
1: Emergency stop interrupt enabled
Bit 2 = ZIM: Back EMF Zero-crossing Interrupt
Mask bit.
0: BEMF Zero-crossing Interrupt disabled
1: BEMF Zero-crossing Interrupt enabled
Bit 1 = DIM: End of Demagnetization Interrupt
Mask bit.
0: End of Demagnetization interrupt disabled
1: End of Demagnetization interrupt enabled if the
Bit 0 = CIM: Commutation / Capture Interrupt
Mask bit
0: Commutation / Capture Interrupt disabled
1: Commutation / Capture Interrupt enabled
PUM
HDM or SDM bit in the MCRB register is set
7
SEM
6
RIM
5
CLIM
4
EIM
3
ST7MC1/ST7MC2
ZIM
2
DIM
1
207/308
CIM
0
1