st7fmc2s7t6 STMicroelectronics, st7fmc2s7t6 Datasheet - Page 218

• Manufacturer Part Number: st7fmc2s7t6
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, Five Timers, Spi, Linsci
• Manufacturer: STMicroelectronics

ST7MC1/ST7MC2
MOTOR CONTROLLER (Cont’d)
REPETITION COUNTER REGISTER (MREP)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = REP[7:0] Repetition counter value (N).
This register allows the user to set-up the update
rate of the PWM counter compare register (i.e. pe-
riodic transfers from preload to active registers),
as well as the PWM Update interrupt generation
rate, if these interrupts are enabled.
Each time the MREP related Down-Counter
reaches zero, the Compare registers are updated,
a U interrupt is generated and it re-starts counting
from the MREP value.
After a microcontroller reset, setting the CKE bit in
the MCRA register (i.e. enabling the clock for the
MTC peripheral) forces the transfer from the
MREP preload register to its active register and
generates a U interrupt. During run-time (while
CKE bit = 1) a new value entered in the MREP
preload register is taken into account after a U
event.
As shown in
to:
– The number of PWM periods in edge-aligned
– The number of half PWM periods in center-
–
COMPARE PHASE W PRELOAD REGISTER
HIGH (MCPWH)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = CPWH[7:0] Most Significant Byte of
phase W preload value
218/308
CPWH
REP7 REP6 REP5 REP4
mode
aligned mode.
7
7
7
CPWH
6
Figure
CPWH
5
CPWH
122, (N+1) value corresponds
4
REP3
CPWH
3
REP2
CPWH
2
REP1
CPWH
1
CPWH
REP0
0
0
0
COMPARE PHASE W PRELOAD REGISTER
LOW (MCPWL)
Read/Write (except bits 2:0)
Reset Value: 0000 0000 (00h)
Bits 7:5 = CPWL[7:3] Low bits of phase W preload
value.
Bits 2:0 = Reserved.
COMPARE PHASE V PRELOAD REGISTER
HIGH (MCPVH)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = CPVH[7:0] Most Significant Byte of
phase V preload value
COMPARE PHASE V PRELOAD REGISTER
LOW (MCPVL)
Read/Write (except bits 2:0)
Reset Value: 0000 0000 (00h)
Bits 7:5 = CPVL[7:3] Low bits of phase V preload
value.
Bits 2:0 = Reserved.
CPVH7 CPVH6 CPVH5 CPVH4 CPVH3 CPVH2 CPVH1 CPVH0
CPVL7 CPVL6 CPVL5 CPVL4 CPVL3
CPWL
7
7
7
7
CPWL
6
CPWL
5
CPWL
4
CPWL
3
-
-
-
-
0
0
0
-
-