st7fmc2s7t6 STMicroelectronics, st7fmc2s7t6 Datasheet - Page 270

• Manufacturer Part Number: st7fmc2s7t6
• Description: 8-bit Mcu With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, Five Timers, Spi, Linsci
• Manufacturer: STMicroelectronics

ST7MC1/ST7MC2
12.11 COMMUNICATION INTERFACE CHARACTERISTICS
12.11.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 147. SPI Slave Timing Diagram with CPHA=0
Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV
4. Depends on f
270/308
OSC
1/t
t
Symbol
t
t
t
su(SS)
w(SCKH)
t
w(SCKL)
t
h(SS)
t
t
t
t
t
t
dis(SO)
t
t
r(SCK)
f(SCK)
t
f
su(MI)
t
v(MO)
h(MO)
MISO
MOSI
su(SI)
a(SO)
v(SO)
h(SO)
h(MI)
c(SCK)
h(SI)
, and T
SCK
SS
1)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
1)
OUTPUT
INPUT
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
CPU
. For example, if f
see note 2
t
Parameter
a(SO)
t
su(SS)
t
su(SI)
4)
CPU
MSB IN
t
t
w(SCKH)
w(SCKL)
MSB OUT
=8MHz, then T
t
t
h(SI)
c(SCK)
Master
f
Slave
f
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
CPU
CPU
t
DD
v(SO)
=8MHz
=8MHz
DD
CPU
,
BIT6 OUT
Conditions
and 0.7xV
= 1/f
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
3)
CPU
DD
=125ns and t
BIT1 IN
.
t
h(SO)
(4 x T
su(SS)
f
t
t
CPU
r(SCK)
f(SCK)
0.0625
see I/O port pin description
Min
CPU
120
100
100
100
100
100
90
=550ns
0
0
0
0
/128
) + 50
LSB IN
LSB OUT
t
h(SS)
f
f
CPU
CPU
Max
120
240
120
120
2
4
/4
/2
t
dis(SO)
Unit
MHz
ns
note 2
see