t71l6808a TM Technology Inc., t71l6808a Datasheet - Page 13

• Manufacturer Part Number: t71l6808a
• Description: Octal 10/100 Switch With Embedded Memory
• Manufacturer: TM Technology Inc.

REFCLK
TXD[1:0][A]
TXD[1:0][B]
TXD[1:0][C]
TXD[1:0][D]
TXD[1:0][E]
TXD[1:0][F]
TXD[1:0][G]
TXD[1:0][H]
TXE[A:H]
RXD[1:0][A]
RXD[1:0][B]
RXD[1:0][C]
RXD[1:0][D]
RXD[1:0][E]
RXD[1:0][F]
RXD[1:0][G]
RXD[1:0][H]
CRSDV[A:H]
RST#
SYSCLK
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
tm
RMII Interface
System Pins
Symbol
CH
TE
I/O
O
O
I
I
I
I
I
68,76,86,92
10,18,28,61
72,79,89,96
7,13,24,58
Pin No.
11,12
14,15
26,27
59,60
69,70
77,78
87,88
93,94
19,20
29,31
62,63
73,74
80,81
90,91
97,98
119
8,9
47
53
Reference Clock.
REFCLK is a 50MHz clock that provides the timing reference
for CRS_DV, RXD[1:0], TX_EN and TXD[1:0].
Transmit Data.
TXD[1:0] shall transition synchronously with respect to
REFCLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY.
Transmit Enable.
TX_EN indicates that the MAC is presenting di-bits on
TXD[1:0] on the RMII for transmission. It shall transmit
synchronously with REFCLK.
Receive Data[1:0].
RXD[1:0] shall transition synchronously to REFCLK. For each
clock period in which CRS_DV is asserted, RXD[1:0] transfers
two bits of recovered data from the PHY.
Carrier Sense/Receive Data Valid.
CRS_DV shall be asserted by the PHY when the receive
medium is non-idle and asserted asynchronously on detection of
carrier due to the criteria relevant to the operating mode.
Reset.
Asynchronous active low reset signal
System Clock.
System clock, 50MHz
Pin Description
P. 13
Function
Preliminary T71L6808A
Publication Date:May. 2001
Revision:0.A