t71l6808a TM Technology Inc., t71l6808a Datasheet - Page 5

• Manufacturer Part Number: t71l6808a
• Description: Octal 10/100 Switch With Embedded Memory
• Manufacturer: TM Technology Inc.

RMII specification signals are as follows,
Signal Name
REFCLK
CRSDV
RXD[1:0]
TXEN
TXD[1:0]
Data Reception
The data reception port will go into the receive-state when CRS in the RMII interface is asserted.
The RMII (Reduced Media Independent Interface) presents the received data in two-bit (di-bit) that
are synchronous to the RMII reference clock (50 MHz). The T71L6808A will then attempt to detect
the occurrence of the SFD (Start Frame Delimiter) pattern “10101011.” All preamble data prior to
SFD are discarded. Once SFD is detected from the RMII interface, the frame data is forwarded and
stored in the buffer of the switch.
Illegal Frames
The T71L6808A will discard all illegal frames such as runt packet (less than 64 bytes), oversize
packet (greater than 1518 or 1522 bytes) and bad CRC.
Frame Forwarding
After a packet is received, both source address (SA) and destination address (DA) are retrieved. The
SA is used to update the port’s address table and the DA is used to determine the frames destination
port. The Address Resolution Logic will attempt to match the destination address with the addresses
stored in the address table and then forwards the packet to the other port, if appropriate.
If the first bit of the destination address is “0,” the frame is regarded as an unicast packet. The
Address Resolution Logic uses address hashing algorithm or direct mapping method to search
destination address and returns a matched destination port number to identify which port the packet
should be forwarded to. If the destination port is within the same VLAN of the receiving port, the
packet will be forwarded. If the destination port does not belong to the VLANs specified at the
receiving ports, the packet will be discarded.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
tm
CH
TE
Direction
(with respect
to the PHY)
Input
Output
Output
Input
Input
Output
Direction
(with respect to
the T71L6808A)
Input
Input
Input
Output
P. 5
Use
Synchronous clock reference for receive,
transmit and control interface.
Carrier Sense/Receive Data Valid
Receive Data
Transmit Enable
Transmit Data
Preliminary T71L6808A
Publication Date:May. 2001
Revision:0.A