isl3873a Intersil Corporation, isl3873a Datasheet

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... I/O drivers. Additional firmware functions specific to access point applications are also available. The ISL3873A has on-board A/Ds and D/A for analog I and Q inputs and outputs, for which the HFA3783 IF QMODEM is recommended. Differential phase shift keying modulation schemes DBPSK and DQPSK, with data scrambling capability, are available along with Complementary Code Keying to provide a variety of data rates ...

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... RXI± ADC 6 RXQ± Q ADC V REF TXI± I DAC 6 TXQ± DAC TX_IF_AGC 7 TX DAC TX_AGC_IN 6 TX ADC RADIO AND SYNTH SERIAL CONTROL 44MHz CLOCK SOURCE † † THE ISL3873A MUST BE SUPPLIED WITH A SEPARATE CLOCK WHEN USB IS USED. ...

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... ISL3873A Signal Descriptions PIN NAME PIN I/O TYPE HA0-9 5V tol, CMOS, Input, 50K Pull Down HCE1- 5V tol, CMOS, Input, 50K Pull Up HCE2- 5V tol, CMOS, Input, 50K Pull Up HD0-15 5V tol, BiDir, 2mA, 50K Pull Down HINPACK- CMOS Output, 2mA HIORD- 5V tol, CMOS, Input, 50K Pull Up ...

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... RXI, ± I RXQ, ± I PIN NAME PIN I/O TYPE TX_AGC_IN I TX_IF_AGC O TXI ± O TXQ ± ISL3873A MAC Radio Interface and General Purpose Port Pins PE1 LE_IF LED1 RADIO_PE LE_RF SYNTHCLK SYNTHDATA PA_PE PE2 CAL_EN TR_SW_BAR TR_SW SERIAL EEPROM PORT PINS SCLK, Serial Clock ...

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... DC Power Supply 2.7 - 3.6V (Not Hardwired Together on Chip) DC Power Supply 2.7 - 3.6V 5V Tolerant DC Power Supply Analog Ground Analog Ground Digital Ground Voltage Reference for A/D’s and D/A’s Current Reference for internal ADC and DAC devices. Requires 12K resistor to ground. ISL3873A Pin Number Assignments SIGNAL NAME PIN NUMBER C7 HD4 F4 C8 HD6 ...

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... DDA P9 GND P10 V SUB P11 VREF P12 V DDA P13 COMPRES2 P14 N C P15 NC P16 NC 6 ISL3873A ISL3873A Pin Number Assignments (Continued) SIGNAL NAME PIN NUMBER D8 HD5 H4 D9 HIREQ H13 D10 HIOWR H14 D11 HOE H15 D12 NC H16 D13 HA5 D14 HWAIT ...

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... RAMCS_ Setup to MWE MA (17..0) Hold from MWE_ Rising Edge RAMCS _ Hold from MWE_ Rising Edge MD (15..0) Setup to MWE_ Rising Edge MD (15..0) Hold from MWE_ Rising Edge SYNTHESIZER SYNTHCLK(PK1) Period 7 ISL3873A Thermal Information Thermal Resistance (Typical, Note 1) +0.5V BGA Package Maximum Storage Temperature Range . . . . . . . . . . -65 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .100 Maximum Lead Temperature (Soldering 10s) ...

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... HREG- Hold Following HIOWR- HWAIT- Delay Falling from HIOWR- HWAIT- Width Time HIOWRN High from HWAIT- High BASEBAND SIGNALS Full Scale Input Voltage (V ) P-P Input Bandwidth (-0.5dB) Input Capacitance Input Impedance (DC) FS (Sampling Frequency) 8 ISL3873A SYMBOL MIN CYC CYC ...

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... Waveforms ADDRESS MA(17..1) RAMCS_ MOE_ t S2 MD(15..0) ADDRESS MA(17..1) RAMCS_ MWE_ MD(15..0) SYNTHCLK SYNLE SPCSPWR t D1 SYNTHDATA 9 ISL3873A FIGURE 1. EXTERNAL MEMORY READ TIMING FIGURE 2. EXTERNAL MEMORY WRITE TIMING CYC t D2 D[n] D[n -1] D[n -2] D[2] FIGURE 3. SYNTHESIZER ...

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... Waveforms (Continued) HA[15:0] HREG- HCE( HIORD- t SUA HINPACK- HWAIT- HD[15:0] HA[15:0] HREGN- HCE ( HIOWR- HWAIT- t SUIOWR HD[15: ISL3873A t t SUREG HREG I t SUCE HCE t WIORD t DIORD t DFINPACK WWT DRWT DFWT FIGURE 4. PC CARD IO READ SUREG HREG t t HCE SUCE t t SUA ...

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... NVCS_ MOE_ MWEL_ MA0/MWEH_ RAMCS_ FIGURE 6. 8-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873A ISL3873A MA1..17 MD0..15 NVCS- MA0/MWEH- MLBE- RAMCS- MOE- MWEL- FIGURE 7. 16-BIT MEMORY INTERFACE REQUIREMENTS FOR ISL3873A 11 ISL3873A SRAM 128Kx8 MD0..7 MA1..17 OE_ WE_ CS_ SRAM 128Kx16 ADDR(0..16) DATA(0..15) UB- ...

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... An access point application could make use of the full address space of the device with 4Mbytes organized 16. The ISL3873A supports 8 or 16-bit code space, and 8 or 16- bit data space. Code space is typically populated with the least expensive Flash memory available, usually an 8-bit device ...

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... HWE-, HOE- HOE- and HWE- are only used to access attribute memory. Common Memory, as specified in the PC Card standard, is not used in the ISL3873A. HOE- is the strobe that enables an attribute memory read cycle. HWE- is the corresponding strobe for the attribute memory write cycle. The attribute space contains the Card Information Structure (CIS) as well as the Function Configuration Registers (FCR) ...

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... Note AN9874, “ISA Plug and Play with the HFA3841” for more details. Register Interface The logical view of the ISL3873A from the host is a block of 32 word wide registers. These appear in IO space starting at the base address determined by the socket controller. There are three types of registers ...

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... USB+ and USB- are the differential pair signals provided for the user. These signals are capable of directly driving a USB cable. USB_DETECT tolerant input to the ISL3873A device used to signal the MAC processor that a USB cable is attached to the unit. Complete details on the USB firmware for controlling this port can be obtained by contacting the factory directly ...

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... This allows proper initialization with omission of either clock source, since without the LF crystal attached there will not be cycles of the LF clock to activate the detection circuit. The ability to initialize the ISL3873A using the LF oscillator to generate MCLK allows the high-frequency (PHY) oscillator to be powered down during sleep state. If this is ...

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... Use the Serial Host Interface (USB), and disable all PC Card functions except attribute space, for access to the COR and HCR for firmware debugging support. When = 0, use the Parallel Host Interface (PC Card or ISA). 12 4Wire 1 Use 4-wire interface to SRAM (CS-, OE-, WEH-, WEL-) the ISL3873A x8 SRAMs. When = 0 selects 5-wire interface for use with x16 SRAM (CS-, OE-, WE-, UBE-, LBE-). 11 StrIdle 0 Start idle (wait for download from PC Card host interface) ...

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... IF down converter device (HFA3783). The I/Q A/D clock, samples at twice the chip rate with a nominal sampling rate of 22MHz. The interface specifications for the I and Q A/Ds are listed in Table 5. The ISL3873A is designed coupled to the HFA3783. TABLE A/D SPECIFICATIONS PARAMETER ...

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... The duration of the short preamble and header is 96µs. Start Frame Delimiter (SFD) Field (16 Bits) This field is used to establish the link frame timing. The ISL3873A will not declare a valid data packet, even acquires, unless it detects the SFD. The ISL3873A receiver auto-detects if the packet is long or short preamble and sets SFD time-out ...

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... See IEEE STD 802.11 for definition of the other bits. Bit 2 is used by the ISL3873A to indicate that the carrier reference and the bit timing references are derived from the same oscillator (locked oscillators). ...

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... CR32 bit NOTE: Be advised that the IEEE 802.11 compliant scrambler in the ISL3873A has the property that it can lock up (stop scrambling) on random data followed by repetitive bit patterns. The probability of this happening is 1/128. The patterns that have been identified are all zeros, all ones, repeated 10s, repeated 1100s, and repeated 111000s ...

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... The CCA circuit in the ISL3873A can be programmed function of RSSI (energy detected on the channel), CS1, SQ1, or various combinations. The CCA is used by the Media Access Controller (MAC) in the ISL3873A. The MAC decides on transmission based on traffic to send and the CCA indication. The CCA indication can be ignored, allowing transmissions independent of any channel conditions ...

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... The AGC system consists of the 3 chips handling the receive signal, the downconverter HFA3683, the IF to baseband converter HFA3783, and the baseband processor (BBP) section of the ISL3873A. The AGC loop (Figure 12) is digitally controlled by the BBP. Basically it operates as follows: Initially, the receiver is set for high gain. The percent of time ...

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... RF chip to switch from high gain to low gain. RX_IF_Det is the input to the ISL3873A chip which is connected to ifCompDet on the HFA3783. RX_RF_AGC is the output of the ISL3873A chip and '1' is high gain, '0' is low gain. Demodulator Description The receiver portion of the baseband processor, performs A/D conversion and demodulation of the spread spectrum signal ...

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... After acquisition, coherent DPSK demodulation is in effect. After a brief setup time as illustrated on the timeline, the signal begins to emerge from the demodulator. 25 ISL3873A 56 SYMBOL SYNC 20 SYMBOLS 7 SYM VERIFY AND CIR/FREQUENCY ESTIMATION AND CMF/NCO ...

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... PN Correlators Description There are two types of correlators in the ISL3873A baseband processor. The first is a parallel matched filter correlator that correlates for the Barker sequence used in preamble, header, and PSK data modes. This Barker code correlator is designed to handle BPSK spreading with carrier offsets up to ± ...

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... The symbol clock is tracked by a sample interpolator that can adjust the sample timing forwards and backwards by 72 increments of 1/8th chip. This approach means that the ISL3873A can only track an offset in timing for a finite interval before the limits of the interpolator are reached. Thus, continuous demodulation is not possible. ...

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... RXQ A/D 6 COHERENT TIMING INTEGRATOR ANTENNA ANTSEL SWITCH ANTSEL CONTROL TIMING GENERATOR MCLK RESET RX_PE FIGURE 19. DSSS BASEBAND PROCESSOR, RECEIVE SECTION 28 ISL3873A GND (ANALOG) V (DIGITAL) DD CLEAR CHANNEL ASSESSMENT/ SIGNAL QUALITY CMF TRAINING 8 PEAK EXTRACT. 8 SYMBOL TRACKING EQUAL. NCO CCK BIAS CORREL ...

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... Figure 21 shows the theoretical and actual performance of the CCK modes. The losses in both figures include RF and IF radio losses; they do not reflect the ISL3873A losses alone. The ISL3873A baseband processing losses from theoretical are, by themselves, a small percentage of the overall loss. The PRISM demodulator performs with an implementation loss of less than 4dB from theoretical in a AWGN environment with low phase noise local oscillators ...

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... A signal quality measure is available on CR51 for use by the MAC. This measure is the SNR in the carrier tracking loop and can be used to determine when the demodulator is working near to the noise floor and likely to make errors. Figure 23 shows the performance of the SQ measure versus signal to noise level. 30 ISL3873A 100 ...

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Control Registers The following tables describe the function of each control register along with the associated bits in each control register. CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE Bit 7:4 Part Code 3 = HFA3863 series Bit 3:0 Version ...

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... Antenna choice for TX when TX antenna diversity is disabled Set AntSel low Set AntSel high. Bit 1 TX Antenna Mode Disable diversity, set AntSel pin to value in bit Enable diversity, set AntSel pin to antenna for which last valid received header CRC occurred. Bit 0 Must be set ISL3873A ...

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... Precursor value in CIR estimate. CONFIGURATION REGISTER 12 ADDRESS (18h) R/W A/D TEST MODES 1 Bit 7 All DAC and A/D clock source control normal internal clocks clock via SDI pin. Bit 6 TX DAC clock enable disable. Bit 5 RX DAC clock enable disable. Bit 4 I DAC clock enable disable. 33 ISL3873A ...

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... CMF weights - upper 6 bits of all 16 CMF weights are circularly shifted with full scale negative sync pulse interleaved between them. 110 = Test Bus pins (5:0) when configured as inputs, CR32(4), ((5:0) to both I and Q inputs). 111 = Barker Correlator/ low rate samples - as selected by bit 7 CR32. 34 ISL3873A ...

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... CONFIGURATION REGISTER 22 ADDRESS (2Ch) R/W AGC LOOKUP TABLE ADDRESS Bits 7,6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bits 5 AGC Look up table read control bit Read AGC table at address given below Read contents of CR23. Bits 4:0 AGC lookup table address (32 address bits). 35 ISL3873A ...

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... CONFIGURATION REGISTER ADDRESS 29 (3Ah) R/W AGC LOCK WINDOW NEGATIVE SIDE Bits 7:5 AGC Saturation Block Level, 1xx.x, range 4.0 to 7.5 dB. Disable saturation attenuation step if less than or equal to this level. Bits 4:0 AGC lock window negative side. (0-15.5 range) (this is the outer lock window) Note: set as a positive number, logic will convert to negative. 36 ISL3873A ...

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... DC offset compensation disable DC offset compensation. Bit 4 Bypass I/Q A/Ds disable bypass MSBs of I/Q data are input on test bus. TESTin 3:0 is [5:2], TESTin 7:4 is Q[5:2], LSBs are zeroed. Bit 3 disable time adjust during packet. Note: this turns off bit tracking normal time tracking disabled (overrides bit 6 also). 37 ISL3873A ...

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... Bits 4:0 SNR threshold #2, range 0 to 31dB. CONFIGURATION REGISTER ADDRESS 40 (50h) R/W DC OFFSET THRESHOLD Bits 7:6 R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions. Bits 5:0 DC offset Threshold, range 0 to 63dB. RSSI > (threshold + NoiseFloor) enables DC offset calculation and compensation. 38 ISL3873A ...

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... Read only register mux control READ ONLY registers read ‘b’ value READ ONLY registers read ‘a’ value. Bits 6:0 Scrambler seed for short preamble. Bit 3 of CR5 selects CR48 or CR49. CONFIGURATION REGISTER ADDRESS 50 (64h) R TEST BUS READ Bit 7:0 a&b: reads value on test bus. 39 ISL3873A ...

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... TX PWR det Register semaphore - a 1 indicates CR58 has updated since last read. Bit 2 a&b: AGC_lock - a 1 indicates AGC is within limits of lock window CR20. Bit 1 a&b: hwStopBHit - a 1 indicates rails hit, AGC updates stopped. Bit 0 a&b: RX_RF_AGC - status of AGC output to RF chip. 40 ISL3873A ...

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... Bit 5 a&b: SFD found. Bit 4 a&b: Short preamble detected. Bit 3 a&b: valid signal field found. Bit 2 a&b: valid CRC 16. Bit 1 a&b: Antenna selected by receiver when last valid header CRC occurred. Bit 0 a&b: not used. 41 ISL3873A CONFIGURATION REGISTER ADDRESS 62 (7Eh) R RSSI ...

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... Intersil Corporation Intersil Corporation 7585 Irvine Center Drive 2401 Palm Bay Rd. Suite 100 Palm Bay, FL 32905 Irvine, CA 92618 TEL: (321) 724-7000 TEL: (949) 341-7000 FAX: (321) 724-7946 FAX: (949) 341-7123 42 ISL3873A A V192.14x14 192 BALL PLASTIC BALL GRID ARRAY PACKAGE SYMBOL D/E D1/E1 ...