isl3873a Intersil Corporation, isl3873a Datasheet - Page 20

• Manufacturer Part Number: isl3873a
• Description: Wireless Lan Integrated Medium Access Controller With Baseband Processor
• Manufacturer: Intersil Corporation

Header Field
The header field is defined by four fields which are shown in
Figure 14. These fields are Signal Field, Service Field,
Length Field and CITT-CRC16 Field. They are further
defined by the following:
Signal Field (8 Bits) - This field indicates what data rate the
data packet that follows the header will be. The ISL3873A
receiver looks at the signal field to determine whether it
needs to switch from DBPSK demodulation into DQPSK, or
CCK demodulation at the end of the preamble and header
fields.
Service Field (8 Bits) - The MSB of this field is used to
indicate the correct length when the length field value is
ambiguous at 11Mbps. See IEEE STD 802.11 for definition
of the other bits. Bit 2 is used by the ISL3873A to indicate
that the carrier reference and the bit timing references are
derived from the same oscillator (locked oscillators).
Length Field (16 Bits) - This field indicates the number of
microseconds it will take to transmit the payload data
(PSDU). The external controller (MAC) will check the length
field in determining when it needs to de-assert RX_PE.
SYMBOL
I vs. Q
Q
RATE
RATE
PREAMBLE (SYNC)
128/56 BITS
DATA
CHIP
I
OUT
OUT
1 BIT ENCODED TO
802.11 DSSS BPSK
(TRUE-INVERSE)
ONE OF 2 CODE
PREAMBLE
11 CHIPS
BARKER
WORDS
11 MC/S
1Mbps
1 MS/S
Start FRAME DELIMITER
16 BITS
20
2 BITS ENCODED
TO ONE OF
4 CODE WORDS
FIGURE 14. 802.11 PREAMBLE/HEADER
802.11 DSSS QPSK
FIGURE 13. MODULATION MODES
SIGNAL FIELD
8 BITS
BARKER
2Mbps
11 CHIPS
11 MC/S
1 MS/S
ISL3873A
SERVICE FIELD
8 BITS
CCITT - CRC 16 Field (16 Bits) - This field includes the
16-bit CCITT - CRC 16 calculation of the three header fields.
This value is compared with the CCITT - CRC 16 code
calculated at the receiver. The ISL3873A receiver will
indicate a CCITT - CRC 16 error via CR24 bit 2 and will
lower MD_RDY and reset the receiver to the acquisition
mode if there is an error.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (Frame Check Sequence). It is the ones complement of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x
The protected bits are processed in transmit order. All CRC
calculations are made ahead of data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected fields are shifted through
the register. The output is then complemented and the
residual shifted out MSB first.
The following Configuration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
16
SPREAD FUNCTIONS
4 BITS ENCODED
+ x
COMPLEX CCK
CODE WORDS
TO ONE OF 16
5.5Mbps CCK
12
COMPLEX
HEADER
1.375 MS/S
+ x
8 CHIPS
11 MC/S
LENGTH FIELD
16 BITS
5
+ 1
CRC16
16 BITS
SPREAD FUNCTIONS
8 BITS ENCODED
COMPLEX CCK
TO ONE OF 256
CODE WORDS
11Mbps CCK
COMPLEX
1.375 MS/S
8 CHIPS
11 MC/S