isl8120 Intersil Corporation, isl8120 Datasheet - Page 24

• Manufacturer Part Number: isl8120
• Description: Dual/n-phase Buck Pwm Controller With Integrated Drivers
• Manufacturer: Intersil Corporation

Both channels share the same PGOOD output. Either of the
channels indicating out-of-regulation will pull-down the
PGOOD pin. The Power-Good comparators monitor the
voltage on the VMON pins. The trip points are shown in
Figure 10. PGOOD will not be asserted until after the
completion of the soft-start cycle of both channels. If
Channels 1 or 2 are not used, the Power-Good can stay in
operation by connecting 2 channels’ VMON pins together.
The PGOOD pulls low upon both EN/FF’s disabling it if one
of the VMON pins’ voltage is out of the threshold window.
PGOOD will not pull low until the fault presents for three
consecutive clock cycles. In Dual/DDR application, if the
turn-off channel pre-charges its VMON within the PGOOD
threshold window, it could indicate Power-Good, however,
the PGOOD signal can pull low with an external PNP or
PMOS transistor via the EN/FF of the corresponding off
channel.
Undervoltage and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection
circuitry monitor the voltage on the VMON pins. The UV
functionality is not enabled until the end of soft-start. An OV
condition (>120%) during soft-start would latch IC off.
In an UV event, if the output drops below -13% (-9% is the
hysteresis level) due to some reasons other than OV, OC,
OT, and PLL faults (EN/FF is not pulled low) of the target
level at the output voltage falling edge, the lower MOSFETs
will turn off to avoid any negative voltage ringing.
An OV event (V
to latch off permanently, while the low-side MOSFET turns
on and then turns off after the output voltage drops below
87%. At the same time, the EN/FF and PGOOD are also
latched low. The latch condition can be reset only by
recycling VCC. In Dual/DDR mode, each channel is
responsible for its own OV event with the corresponding
VMON as the monitor. In multiphase mode, both channels
respond simultaneously when either triggers an OV event.
VMON2>120%
EN/FF2
VMON1
EN/FF1
VMON1>120%
VMON2
87%
87%
113%
113%
FIGURE 11. FORCE LGATE HIGH LOGIC
OUT
multiphase
MODE = HIGH
> 120%) causes the high-side MOSFET
OR
OR
24
OR
AND
AND
AND
FORCE
LGATE1
HIGH
FORCE
LGATE2
HIGH
ISL8120
To protect the overall power trains in case of only one
channel of a multiphase system detecting OV, the low-side
MOSFET always turns on at the conditions of EN/FF = LOW
and the output voltage above 113% (all VMON pins and EN
pins are tied together) and turns off after the output drops
below 87%. Thus, in a high phase count application
(Multiphase Mode), all cascaded ICs can latch off
simultaneously via EN pins, and each IC shares the same
sink current to reduce the stress and eliminate the bouncing
among phases.
PRE-POR Overvoltage Protection (PRE-POR-OVP)
When both the VCC and PVCC are below PORs (not include
EN POR), the UGATE is low and LGATE is floating (high
impedance). EN/FF has no control on LGATE when below
PORs. When above PORs, the LGATE would not be floating
but toggling with its PWM pulses. An external 10Ω resistor,
connected in between Phase and LGATE nodes, enables
the PRE-POR-OVP circuit. The output of the converter that
is equal to phase node voltage via output inductors is then
effectively clamped to the low-side MOSFET’s gate
threshold voltage, which provides some protection to the
microprocessor if the upper MOSFET(s) is shorted during
startup, shutdown, or normal operations. For complete
protection, the low-side MOSFET should have a gate
threshold that is much smaller than the maximum voltage
rating of the load.
The PRE-POR-OVP works against pre-biased start-up when
pre-charged output voltage is higher than threshold of
low-side MOSFET, however, it can be disabled by placing a
2k to10Ω resistor from LGATE to ground.
Over-Temperature Protection (OTP)
When the junction temperature of the IC is greater than
+160°C (typically), both EN/FF pins pull low to inform other
cascaded channels via their EN/FF pins. All connected
EN/FFs stay low and release after the IC’s junction
temperature drops below +125°C (typically), with a +35°C
hysteresis (typical).
VOUT
PGOOD
FIGURE 12. UV AND OV TIMING DIAGRAM
3 CYCLES
3 CYCLES
UGATE AND EN/FF LATCH LOW
UV
120%
OV LATCH
March 28, 2008
FN6641.0