isl8120 Intersil Corporation, isl8120 Datasheet - Page 27

• Manufacturer Part Number: isl8120
• Description: Dual/n-phase Buck Pwm Controller With Integrated Drivers
• Manufacturer: Intersil Corporation

channels’ error amplifiers should be disabled with their
corresponding VSEN- pulled to VCC, as shown in Figure 15.
Current Share Control Loop in Multi-Module with
Independent Voltage Loop
The power module controlled by ISL8120 with its own
voltage loop can be paralleled to supply one common output
load with its integrated Master-Slave current sharing control,
as shown in “Typical Application VIII (Multiple Power
Modules in Parallel with Current Sharing Control)” on
page 12. A resistor R
VSEN1- pin and the lower resistor of the voltage sense
resistor divider for each module. With this resistor, the
correction current sourcing from VSEN1- pin will create a
voltage offset to maintain even current sharing among
modules. The recommended value for the VSEN1- resistor
R
unity gain amplifier input pin impedance compatibility. The
maximum source current from VSEN1- pin is 350µA, which
is combined with R
regulation range. The generated correction voltage on R
is suggested to be within 5% of VREF (0.6V) to avoid fault
trigging of UV/OV and PGOOD during dynamic events.
To attain good current balance in system start up preventing
single module from overcurrent, the paralleled modules are
recommended to be synchronized and the enable pins
(EN/FF) should be tied together to initial startup at the same
instant.
Overcurrent Protection
The OCP function is enabled at startup. When both channels
operate independently, the average function is disabled and
generates zero average current (I
current (I
own independent overcurrent protection; while the 7 clock
cycles delay is bypassed. The channel 1’s current (I
CSR
is 100Ω and it should not be large in order to keep the
R
ISET1
CS2
) is compared with I
CSR
CSR
ISET
VSEN1/2- COM1/2
to determine the current sharing
ISHARE
ISL8120
needs to be inserted between
27
R
FIGURE 15. SIMPLIFIED 6-PHASE SINGLE OUTPUT IMPLEMENTATION
ISHARE1
TRIP
1
AVG
(105µA) and has its
= 0). The channel 2
SHARE BUS
R
ISET2
CS1
CSR
)
ISET
R
VSEN2-
ISHARE_
ISL8120
ISHARE
ISL8120
VCC
R
COM1/2
= R
ISHARE2
2
ISET_
plus 15µA offset forms a voltage (V
resistor R
threshold (±1%, 50mV hysteresis); while the 105µA OCP
comparator with 7-cycle delay is also activated.
In multiphase operation, the V
average current of all active channels and compares with a
precision 1V threshold (±1%, 50mV hysteresis) to determine
the overcurrent condition, while each channel has additional
overcurrent trip point at 105µA with 7-cycle delay. This
scheme helps protect against loss of channel(s) in
multi-phase mode so that no single channel could carry
more than 105µA in such event. See Figure 13. Note that it
is not necessary for the R
same level as the 105µA OCP comparator if the application
allows. For instance, when Channel 1 operates
independently, the OC trip set by 1V comparator can be
lower than 105µA trip point as shown in Equation 6.
where N is the number of phases; N
the ISL8120 controllers in parallel or multiphase operations;
I
T
R
equivalent resistance in ISHARE pin bus of all ICs in
multiphase or module parallel operation.
The overcurrent trip current source is trimmed to 105µA
±10% for both channels, while the overcurrent threshold
(represented by V
R
TRIP
R
MIN_OFF
ISHARE
ISHARE
ISEN1
=105µA; I
VSEN1-
VSEN1+
=
ISHARE
in Equation page 27 represents the total
=
is the minimum Ugate turn off time that is 350ns;
⎛
⎜
⎝
----------------------------------------------------------------------------------------------------------------------- -
I
--------- -
-------------- -
I
OC
N
TRIP
1V
OC
+
V
--------------- -
and compares with a precision 1V
ISHARE
OUT
is the load over current trip point;
L
ISET
•
VSEN1/2- COM1/2
R
⎛
⎝
) for multiphase operation (or
ISHARE
ISET
--------------- - T
2F
1 D
ISHARE
–
ISL8120
SW
I
TRIP
ISHARE
=
R
–
ISHARE3
R
to be scaled to trip at the
ISHARE
3
ISHARE
MIN_OFF
CNTL
represents the
is the number of
⋅
) with an external
⎞
⎠
N
⎞
⎟
⎠
CNTL
•
R
DCR
ISET3
March 28, 2008
(EQ. 6)
FN6641.0