isl9444 Intersil Corporation, isl9444 Datasheet - Page 17

• Manufacturer Part Number: isl9444
• Manufacturer: Intersil Corporation

A resistive divider from the output to ground sets the output
voltage of any PWM channel. The center point of the divider shall
be connected to the FBx pin. The output voltage value is
determined by Equation 5.
Where R1 is the top resistor of the feedback divider network and
R2 is the bottom resistor connected from FBx to ground.
Tracking Operation
The PWM2 and PWM3 of the ISL9444 can be independently set
up to track the output of another PWM or an external supply. In
the following discussion, we refer to the voltage rail to be tracked
as the master rail while we refer to the voltage rail that follows
the master as the slave rail. To implement tracking, an additional
resistive divider is connected between the master rail and
ground. The center point of the divider shall be connected to the
TK/SSx pin of the slave PWM. The resistive divider ratio sets the
ramping ratio between the two voltage rails. To implement
coincident tracking, set the tracking resistive divider ratio exactly
the same as the slave rail output resistive divider given by
Equation 5. Make sure that the voltage at TK/SSx is greater than
0.7V when the master rail reaches regulation.
To minimize the impact of the 1.55µA soft-start current on the
tracking function, it is recommended to use resistors of less than
10kΩ for the tracking resistive dividers.
When overcurrent protection (OCP) is triggered for the slave PWM
channel, the internal minimum soft-start circuit determines the
OCP soft-start hiccup.
Light Load Efficiency Enhancement
When MODE/SYNC is tied to GND, the ISL9444 operates in high
efficiency diode emulation mode and pulse skipping mode in
light load condition. The inductor current is not allowed to reverse
(discontinuous operation). At very light loads, the converter goes
into diode emulation and triggers the pulse skipping function.
Here, the upper MOSFET remains off until the output voltage
drops to the point the error amplifier output goes above the pulse
skipping mode threshold.
The minimum t
select frequency so that the PWM t
maximum VIN at no load.
Pre-biased Power-up
The ISL9444 has the ability to soft-start with a pre-biased output.
The output voltage would not be yanked down during pre-biased
start-up. The PWM is not active until the soft-start ramp reaches
the output voltage times the resistive divider ratio.
Overvoltage protection is alive during soft-starting.
Frequency Selection
Switching frequency selection is a trade-off between efficiency
and component size. Low switching frequency improves
efficiency by reducing MOSFET switching loss. To meet output
ripple and load transient requirements, operation at a low
switching frequency would require larger inductance and output
V
OUTx
=
0.7V
⎛
⎝
R1
--------------------- -
ON
R2
+
in the pulse skipping mode is 80ns; please
R2
⎞
⎠
17
ON
is greater than 80ns at
(EQ. 5)
ISL9444
capacitance. The switching frequency of the ISL9444 is set by a
resistor connected from the RT pin to GND according to
Equation 1.
Frequency setting curve shown in Figure 26 assists in selecting
the correct value for R
Frequency Synchronization
The MODE/SYNC pin may be used to synchronize two or more
ISL9444 or ISL9443 controllers. When the MODE/SYNC pin is
connected to the CLKOUT pin of another ISL9444, the two
controllers operate in synchronization.
When the MODE/SYNC pin is connected to an external clock, the
ISL9444 will synchronize to this external clock at half of the clock
frequency. For proper operation, frequency setting resistor, R
should be set according to Equation 1.
When frequency synchronization is in action, the controllers will
enter forced continuous current mode at light load.
Out-of-Phase Operation
To reduce input ripple current, the three PWM channels operate
180° out-of-phase. This reduces the input capacitor ripple current
requirements, reduces power supply-induced noise, and improves
EMI. This effectively helps to lower component cost, save board
space and reduce EMI.
Triple PWMs traditionally operate in-phase and turn on all three
upper FETs at the same time. The input capacitor must then support
the instantaneous current requirements of the three switching
regulators simultaneously, resulting in increased ripple voltage and
current. The higher RMS ripple current lowers the efficiency due to
the power loss associated with the ESR of the input capacitor. This
typically requires more low-ESR capacitors in parallel to minimize
the input voltage ripple and ESR-related losses, or to meet the
required ripple current specification.
With synchronized out-of-phase operation, the high-side
MOSFETs turn off 180° out-of-phase. The instantaneous input
current peaks of both regulators no longer overlap, resulting in
reduced RMS ripple current and input voltage ripple. This
reduces the required input capacitor ripple current rating,
1250
1000
750
500
250
0
0
FIGURE 26. R
20
40
T
.
T
60
vs SWITCHING FREQUENCY
80
R
T
(kΩ)
100
120
140
160
May 23, 2011
FN7665.0
180
T
,