isl9444 Intersil Corporation, isl9444 Datasheet - Page 21

• Manufacturer Part Number: isl9444
• Manufacturer: Intersil Corporation

10. Route all high speed switching nodes away from the control
11. Create a separate small analog ground plane near the IC.
12. Separate current sensing traces from PHASE node
13. Ensure the feedback connection to the output capacitor is
General PowerPAD Design Considerations
The following is an example of how to use vias to remove heat
from the IC.
It is recommended to fill the thermal pad area with vias. A typical
via array fills the thermal pad footprint such that their centers are
3x the radius apart from each other. Keep the vias small but not
so small that their inside diameter prevents solder wicking
through during reflow.
Connect all vias to the ground plane. It is important the vias have
a low thermal resistance for efficient heat transfer. It is
important to have a complete connection of the plated-through
hole to each plane.
Component Selection Guideline
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency given
the potentially wide input voltage range and output power
requirements. Two N-Channel MOSFETs are used in each of the
synchronous-rectified buck converters for the 3 PWM outputs.
These MOSFETs should be selected based upon r
supply requirements, and thermal management considerations.
Power dissipation includes two loss components: conduction
loss and switching loss. These losses are distributed between
the upper and lower MOSFETs according to duty cycle (see
Equations 14 and 15). The conduction losses are the main
component of power dissipation for the lower MOSFETs. Only the
upper MOSFET has significant switching losses, since the lower
voltages, the stray capacitor formed between these islands
and the surrounding circuitry will tend to couple switching
noise.
circuitry.
Connect the SGND pin to this plane. All small signal grounding
paths including feedback resistors, current limit setting
resistors, soft-starting capacitors and ENx pull-down resistors
should be connected to this SGND plane.
connections.
short and direct.
FIGURE 29. PCB VIA PATTERN
21
DS(ON)
, gate
ISL9444
device turns on and off into near zero voltage. The equations
assume linear voltage-current transitions and do not model
power loss due to the reverse-recovery of the lower MOSFET’s
body diode.
P
P
A large gate-charge increases the switching time, t
increases the upper MOSFETs’ switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at high
ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications.
Output Inductor Selection
The PWM converters require output inductors. The output
inductor is selected to meet the output voltage ripple
requirements. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current and the output capacitor(s) ESR. The ripple voltage
expression is given in the capacitor selection section and the
ripple current is approximated by Equation 16:
ΔI
Output Capacitor Selection
The output capacitors for each output have unique requirements.
In general, the output capacitors should be selected to meet the
dynamic regulation requirements including ripple voltage and
load transients. Selection of output capacitors is also dependent
on the output inductor, so some inductor analysis is required to
select the output capacitors.
One of the parameters limiting the converter’s response to a load
transient is the time required for the inductor current to slew to
its new level. The ISL9444 will provide either 0% or maximum
duty cycle in response to a load transient.
The response time is the time interval required to slew the
inductor current from an initial current value to the load current
level. During this interval, the difference between the inductor
current and the transient current level must be supplied by the
output capacitor(s). Minimizing the response time can minimize
the output capacitance required. Also, if the load transient rise
time is slower than the inductor response time, as in a hard
drive or CD drive, it reduces the requirement on the output
capacitor.
The maximum capacitor value required to provide the full, rising
step, transient load current during the response time of the
inductor is:
C
Where C
inductor, I
OUT
UPPER
LOWER
L
=
=
(
-------------------------------------------------- -
V
---------------------------------------------------- -
2 V
=
IN
OUT
=
(
( ) L ( ) V
TRAN
f
(
--------------------------------------------------------- -
–
(
------------------------------------------------------------------------
S
(
I
IN
I
L
O
V
is the output capacitor(s) required, L
O
O
2
OUT
2
–
) I
) r
) r
is the transient load current step, V
(
V
(
(
(
O
TRAN
DS ON
) V
DS ON
(
) DV
IN
(
V
(
(
OUT
)
IN
)
V
OUT
2
)
)
IN
)
) V
) V
(
(
)
OUT
IN
–
)
V
+
OUT
( ) V
------------------------------------------------------- -
I
O
)
(
IN
) t
(
2
SW
) F
(
O
SW
IN
is the output
SW
)
is the input
, which
May 23, 2011
FN7665.0
(EQ. 14)
(EQ. 15)
(EQ. 16)
(EQ. 17)