isl9444 Intersil Corporation, isl9444 Datasheet - Page 20

• Manufacturer Part Number: isl9444
• Manufacturer: Intersil Corporation

up to 100µA can be used. A higher sampling current will help to
stabilize the loop.
Due to the current loop feedback, the modulator has a single pole
response with -20dB slope at a frequency determined by the load.
F
Where R
type of modulator, a Type 2 compensation circuit is usually
sufficient.
Figure 28 shows a Type 2 amplifier and its response, along with
the responses of the current mode modulator and the converter.
The Type 2 amplifier, in addition to the pole at origin, has a
zero-pole pair that causes a flat gain region at frequencies
between the zero and the pole.
Zero frequency, amplifier high-frequency gain and modulator
gain are chosen to satisfy most typical applications. The
crossover frequency will appear at the point where the modulator
attenuation equals the amplifier high frequency gain. The only
task that the system designer has to complete is to specify the
output filter capacitors to position the load main pole
somewhere within one decade lower than the amplifier zero
frequency. With this type of compensation, plenty of phase
margin is easily achieved due to zero-pole pair phase ‘boost’.
Conditional stability may occur only when the main load pole is
positioned too much to the left side on the frequency axis due to
excessive output filter capacitance. In this case, the ESR zero
placed within the 1.2kHz to 30kHz range gives some additional
phase ‘boost’. Some phase boost can also be achieved by
connecting capacitor C
the divider that sets the output voltage value. Please refer to
“Input Capacitor Selection” on page 22.
F
F
PO
Z
P
MODULATOR
G
=
=
M
=
----------------------------- -
2π R
----------------------------- -
2π R
= 17.5dB
------------------------------
2π R
O
⋅
⋅
EA
⋅
1
is load resistance and C
1
FIGURE 28. FEEDBACK LOOP COMPENSATION
F
2
1
1
CONVERTER
PO
O
⋅
⋅
C
C
⋅
C
1
2
O
=
=
10kHz
600kHz
Z
in parallel with the upper resistor R
F
20
Z
O
R1
is load capacitance. For this
F
C
G
EA
TYPE 2 EA
= 18dB
R2
C2
C1
F
P
(EQ. 11)
(EQ. 12)
(EQ. 13)
ISL9444
1
of
Layout Guidelines
Careful attention to layout requirements is necessary for
successful implementation of an ISL9444 based DC/DC
converter. The ISL9444 switches at a very high frequency and
therefore the switching times are very short. At these switching
frequencies, even the shortest trace has significant impedance.
Also, the peak gate drive current rises significantly in an
extremely short time. Transition speed of the current from one
device to another causes voltage spikes across the
interconnecting impedances and parasitic circuit elements.
These voltage spikes can degrade efficiency, generate EMI,
increase device overvoltage stress and ringing. Careful
component selection and proper PC board layout minimizes the
magnitude of these voltage spikes.
There are three sets of critical components in a DC/DC converter
using the ISL9444: The controller, the switching power
components and the small signal components. The switching
power components are the most critical from a layout point of
view because they switch a large amount of energy so they tend
to generate a large amount of noise. The critical small signal
components are those connected to sensitive nodes or those
supplying critical bias currents. A multi-layer printed circuit board
is recommended.
Layout Considerations
1. The input capacitors, upper FET, lower FET, inductor and
2. Use separate ground planes for power ground and small
3. The loop formed by the input capacitor, the top FET and the
4. Ensure the current paths from the input capacitor to the
5. Place the PWM controller IC close to the lower FET. The LGATE
6. Place VCC_5V bypass capacitor very close to VCC_5V pin of
7. Place the gate drive components - optional BOOT diode and
8. The output capacitors should be placed as close to the load as
9. Use copper filled polygons or wide but short trace to connect
output capacitor should be placed first. Isolate these power
components on the topside of the board with their ground
terminals adjacent to one another. Place the input high
frequency decoupling ceramic capacitors very close to the
MOSFETs.
signal ground. Connect the SGND and PGND together close to
the IC. Do not connect them together anywhere else.
bottom FET must be kept as small as possible.
MOSFET, to the output inductor and output capacitor are as
short as possible with maximum allowable trace widths.
connection should be short and wide. The IC can be best
placed over a quiet ground area. Avoid switching ground loop
currents in this area.
the IC and connect its ground to the PGND plane.
BOOT capacitors - together near controller IC.
possible. Use short wide copper regions to connect output
capacitors to load to avoid inductance and resistances.
the junction of upper FET, lower FET and output inductor. Also
keep the PHASE node connection to the IC short. Do not
unnecessarily oversize the copper islands for PHASE node.
Since the phase nodes are subjected to very high dv/dt
May 23, 2011
FN7665.0