isl6341a Intersil Corporation, isl6341a Datasheet - Page 11

• Manufacturer Part Number: isl6341a
• Description: 5v Or 12v Single Synchronous Buck Pulse-width Modulation Pwm Controller
• Manufacturer: Intersil Corporation

Switching Frequency
The switching frequency is a fixed 300kHz for the ISL6341,
and 600kHz for the ISL6341A, ISL6341B. It cannot be
adjusted externally, and the various soft-start delays and
ramps are fixed at the same times for either frequency.
Output Voltage Selection
The output voltage can be programmed to any level between
the 0.8V internal reference, up to the V
85% duty cycle restriction for the ISL6341 (75% for the
ISL6341A, ISL6341B). Additional duty cycle margin due to
the r
needs to be factored in as well.
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See the “Typical
Application” schematic on page 3 for more detail; R
upper resistor; R
lower one. The recommended value for R
(±1% for accuracy) and then R
to Equation 2. Since R
(see “Feedback Compensation” on page 12), it is often
easier to change R
that way the compensation calculations do not need to be
repeated. If V
Output voltages less than 0.8V are not available.
V
R
OCP (41/41B) V OUT latches off;
OCP
(41A)
UVP
(-25%)
OVP
(+25%)
PGOOD
(UV; -10%)
PGOOD
(OV; +10%)
PGOOD
(OCP)
PROTECTION
OUT
O
=
DS(ON)
=
----------------------------------
V
R
OUT
0.8V
S
•
0.8V
–
drop across the upper FET at maximum load
•
OUT
0.8V
(
---------------------------
TABLE 2. PROTECTION SUMMARY
R
LGATE and UGATE low.
Infinite retries; wait ~10ms,
and try a new Soft-Start ramp.
V OUT latches off;
LGATE and UGATE low.
V OUT latches off;
UGATE low;
LGATE goes low and high to
keep V OUT within 50% and
125% of nominal.
VOS pin open will trigger OV.
PGOOD goes low if VOS is
10% too low.
PGOOD goes low if VOS is
10% too high.
PGOOD goes low if OCP trips after SS
S
OFFSET
R
+
= 0.8V, then R
OFFSET
O
R
ACTION TAKEN
O
S
)
is part of the compensation circuit
(shortened to R
to change the output voltage;
11
OFFSET
OFFSET
IN
is chosen according
O
supply, with the
S
can be left open.
POR or
COMP/EN
POR or
COMP/EN
after SS
ramp
POR
after SS
ramp
after SS
ramp
ramp
ENABLED
below) is the
is 1kΩ to 5kΩ
ISL6341, ISL6341A, ISL6341B
AFTER
S
is the
(EQ. 2)
POR or
COMP/EN
Not
Applicable
POR
POR
POR or
COMP/EN
POR or
COMP/EN
POR or
COMP/EN
or good
SS ramp
RESET
BY
The VOS pin is expected to see the same ratio for its resistor
divider; R
(±1% for accuracy) range. To simplify the BOM, R
should match R
Input Voltage Considerations
The “Typical Application” diagram on page 3 shows a
standard configuration where V
includes the standard 5V (±10%) or 12V (±20%) power
supply ranges. The gate drivers use the V
LGATE, and V
is an internal 5V regulator for bias.
The V
as V
sources, such as outputs of other regulators. If V
up first, and the V
initialization is done, then undervoltage will trip at the end of
soft-start (and will not recover without toggling V
COMP/EN will not restart it). Therefore, either the supplies
must be turned on in the proper order (together, or V
or the COMP/EN pin should be used to disable V
supplies are ready.
Figure 10 shows a simple sequencer for this situation. If V
powers up first, Q
Q
shut-down. When V
R
release the shut-down. If V
turning Q
start-up as soon as V
is 0.7V nominal, so a wide variety of NFET’s or NPN’s or
even some logic IC’s can be used as Q
be low leakage when off (open-drain or open-collector) so as
not to interfere with the COMP output. Q
placed near the COMP/EN pin.
The V
the 0.8V reference). It can be as high as 20V (for V
below V
some restrictions for running high V
The first consideration for high V
voltage of 36V. The V
voltage - minus the diode drop), plus any ringing (or other
transients) on the BOOT pin must be less than 36V. If V
20V, that limits V
2
2
determines when Q
on, keeping the ISL6341, ISL6341A, ISL6341B in
CC
IN
IN
, but can also run off a separate supply or other
IN
to the upper MOSFET can share the same supply
range can be as low as ~1.5V (for V
2
VOS1
, limited by the maximum duty cycle). There are
off; so the ISL6341, ISL6341A, ISL6341B will
FIGURE 10. SEQUENCER CIRCUIT
GD
should also be chosen in the 1kΩ to 5kΩ
S
GD
R
R
, and R
IN
1
(also 5V to 12V) for BOOT/UGATE. There
1
2
V
will be off and R
IN
IN
or V
plus ringing to 16V.
IN
CC
turns on, the resistor divider R
1
(as seen on PHASE) plus V
VOS2
GD
turns on, which will turn off Q
comes up. The V
R
Q
3
1
IN
V
CC
are not present by the time the
powers up first, Q
should match R
CC
IN
to COMP/EN
Q
2
is 5V to 12V, which
is the maximum BOOT
3
IN
pulling to V
voltage.
1
2
or Q
CC
ENABLE
should also be
OUT
2
voltage for
OFFSET
; but Q
1
CC
OUT
CC
CC
August 20, 2007
will be on,
VOS1
as low as
trip point
; toggling
OUT
GD
CC
will turn
powers
1
until all
2
FN6538.0
2
.
and
, and
(boot
must
last),
IN
just
CC
is