ds3171n Maxim Integrated Products, Inc., ds3171n Datasheet - Page 15

• Manufacturer Part Number: ds3171n
• Description: Ds3171, Ds3172, Ds3173, Ds3174 Single/dual/triple/quad Ds3/e3 Single-chip Transceivers
• Manufacturer: Maxim Integrated Products, Inc.

3.10 Trail Trace Buffer Features
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3.11 Bit Error Rate Tester (BERT) Features
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3.12 Loopback Features
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3.13 Microprocessor Interface Features
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3.14 Test Features
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Each port has a dedicated Trail Trace Buffer for E3-G.832 link management
Extraction and storage of the incoming G.832 trail access point identifier in a 16-byte receive register
Insertion of the outgoing trail access point identifier from a 16-byte transmit register
Receive trace identifier unstable status indication
Each port has a dedicated BERT tester
Generation and detection of pseudo-random patterns and repetitive patterns from 1 to 32 bits in length
Pattern insertion/extraction in DS3/E3 payload or entire data stream to and from the line interface
Large 24-bit error counter allows testing to proceed for long periods without host intervention
Errors can be inserted in the generated BERT patterns for diagnostic purposes (single bit errors or specific bit-
error rates)
Analog interface loopback – ALB (transmit to receive)
Line facility loopback – LLB (receive to transmit) with optional transmission of unframed all-one AIS payload
toward system/trunk interface
Framer diagnostic loopback – DLB (transmit to receive) with automatic transmission of DS3 AIS or unframed
all-one AIS signal toward line/tributary interface(s)
DS3/E3 framer payload loopback – PLB (receive to transmit) with optional transmission of unframed all-one
AIS payload toward system/trunk interface
Simultaneous line facility loopback and framer diagnostic loopback
Multiplexed or non-multiplexed address bus modes
8-bit or 16-bit data bus modes
Byte swapping option in 16-bit data bus mode
Read/Write and Data Strobe modes
Ready handshake output signal
Global reset input pin
Global interrupt output pin
Two programmable I/O pins per port
Five pin JTAG port
All functional pins are inout pins in JTAG mode
Standard JTAG instructions: SAMPLE/PRELOAD, BYPASS, EXTEST, CLAMP, HIGHZ, IDCODE
RAM BIST on all internal RAM
Hi-Z pin to force all digital output and inout pins into HIZ
TEST pin for manufacturing scan test modes
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