ds3171n Maxim Integrated Products, Inc., ds3171n Datasheet - Page 204
ds3171n
Manufacturer Part Number
ds3171n
Description
Ds3171, Ds3172, Ds3173, Ds3174 Single/dual/triple/quad Ds3/e3 Single-chip Transceivers
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS3171N.pdf
(234 pages)
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 10: Remote Error Indication Interrupt Enable (FBEIE) – This bit enables an interrupt if the FBEL bit is set
and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 9: Parity Error Interrupt Enable (PEIE) – This bit enables an interrupt if the PEL bit is set and the bit in
GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 8: Framing Error Interrupt Enable (FEIE) – This bit enables an interrupt if the FEL bit is set and the bit in
GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 2: Remote Error Indication Count Interrupt Enable (FBECIE) – This bit enables an interrupt if the FBECL bit
is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 1: Parity Error Count Interrupt Enable (PECIE) – This bit enables an interrupt if the PECL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Framing Error Count Interrupt Enable (FECIE) – This bit enables an interrupt if the FECL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
15
--
--
0
7
0
14
--
--
0
6
0
E3G832.RSRIE2
E3 G.832 Receive Status Register Interrupt Enable #2
(1,3,5,7)2Eh
13
--
--
0
5
0
12
--
--
0
0
4
204
Reserved
Reserved
11
0
3
0
FBECIE
FBEIE
10
0
2
0
PECIE
PEIE
9
0
1
0
FECIE
FEIE
8
0
0
0
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