ds3171n Maxim Integrated Products, Inc., ds3171n Datasheet - Page 169

• Manufacturer Part Number: ds3171n
• Description: Ds3171, Ds3172, Ds3173, Ds3174 Single/dual/triple/quad Ds3/e3 Single-chip Transceivers
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 2: Receive FEAC FIFO Overflow Interrupt Enable (RFFOIE) – This bit enables an interrupt if the RFFOL bit
is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 1: Receive FEAC Codeword Detect Interrupt Enable (RFCDIE) – This bit enables an interrupt if the RFCDL
bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Receive FEAC Idle Interrupt Enable (RFIIE) – This bit enables an interrupt if the RFIL bit is set and the bit
in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 7: Receive FEAC FIFO Data Invalid (RFFI) – When 0, the Receive FIFO data (RFF[5:0]) is valid. When 1, the
Receive FIFO data is invalid (Receive FIFO is empty).
Bits 5 to 0: Receive FEAC FIFO Data (RFF[5:0]) – These six bits are the FEAC code data stored in the Receive
FIFO. RFF[5] is the LSB (last bit received) of the FEAC code (C[6]), and RFF[0] is the MSB (first bit received) of the
FEAC code (C[1]). The Receive FEAC FIFO data (RFF[5:0]) is updated when it is read (lower byte read).
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
RFFI
15
15
--
--
--
0
7
0
0
7
0
14
14
--
--
--
--
0
6
0
0
6
0
FEAC.RSRIE
FEAC Receive Status Register Interrupt Enable
(0,2,4,6)D8h
FEAC.RFDR
FEAC Receive FIFO Data Register
(0,2,4,6)DCh
RFF5
13
13
--
--
--
0
5
0
0
5
0
RFF4
12
12
--
--
0
0
--
0
0
4
4
169
RFF3
11
11
--
--
--
0
3
0
0
3
0
RFFOIE
RFF2
10
10
--
--
0
2
0
0
2
0
RFCDIE
RFF1
--
--
9
0
1
0
9
0
1
0
RFIIE
RFF0
--
--
8
0
0
0
8
0
0
0