SB16C1058-TQFP128 IK Semicon Co., Ltd, SB16C1058-TQFP128 Datasheet - Page 38

• Manufacturer Part Number: SB16C1058-TQFP128
• Description: Octal-uart Controller With 256-byte Fifo
• Manufacturer: IK Semicon Co., Ltd

IN16C1058
OCTAL UART WITH 256-BYTE FIFO
JUNE 2009
38
REV 1.0
7.6 Line Control Register (LCR, Page 0)
LCR controls the asynchronous data communication format. The word length, the number
of stop bits, and the parity type are selected by writing the appropriate bits to the LCR.
Table 13 shows LCR bit settings.
Table 13:
Bit
7
6
5
4
3
2
1:0
Symbol
LCR[7]
LCR[6]
LCR[5]
LCR[4]
LCR[3]
LCR[2]
LCR[1:0]
Line Control Register Description
Description
Divisor Latch Enable.
Break Enable.
Set Stick Parity.
Parity Type Select.
Parity Enabled.
Number of Stop Bits.
Word Length Bits.
0 : Disable the divisor latch (default).
1 : Enable the divisor latch.
0 : No TX break condition output (default).
1 : Forces TXD output to ‘0’, for alerting the communication
LCR[5:3] = xx0 : No parity is selected.
LCR[5:3] = 0x1 : Stick parity disabled. (default)
LCR[5:3] = 101 : Stick parity is forced to ‘1’.
LCR[5:3] = 111 : Stick parity is forced to ‘0’.
LCR[5:3] =001 : Odd parity is selected.
LCR[5:3] =011 : Even parity is selected.
0 : No parity (default).
1 : A parity bit is generated during the transmission and
LCR[2:0] = 0xx : 1 stop bit (word length = 5, 6, 7, 8).
LCR[2:0] = 100 : 1.5 stop bits (word length = 5).
LCR[2:0] = 11x or 1x1 : 2 stop bits (word length = 6, 7. 8).
00 : 5 bits (default).
01 : 6 bits.
10 : 7 bits.
11 : 8 bits.
terminal to a line break condition.
the receiver checks for receive parity.