SB16C1058-TQFP128 IK Semicon Co., Ltd, SB16C1058-TQFP128 Datasheet - Page 40

• Manufacturer Part Number: SB16C1058-TQFP128
• Description: Octal-uart Controller With 256-byte Fifo
• Manufacturer: IK Semicon Co., Ltd

IN16C1058
OCTAL UART WITH 256-BYTE FIFO
JUNE 2009
40
REV 1.0
7.8 Line Status Register (LSR, Page 0)
Table 15:
Bit
7
6
5
4
3
2
1
0
LSR provides the status of data transfers between the UART and the CPU. When LSR is
read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the top of the RX
FIFO. The errors in a character are identified by reading LSR and then reading RBR.
Reading LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RBR. Table 15 shows LSR bit settings.
Symbol
LSR[7]
LSR[6]
LSR[5]
LSR[4]
LSR[3]
LSR[2]
LSR[1]
LSR[0]
Line Status Register Description
Description
RX FIFO data error Indicator.
THR and TSR Empty Indicator.
THR Empty Indicator.
Break Interrupt Indicator.
Framing Error Indicator.
Parity Error Indicator.
Overrun Error Indicator.
Receive Data Ready Indicator.
0 : No RX FIFO error (default).
1 : At least one parity error, framing error, or break indication is in the
0 : THR or TSR is not empty.
1 : THR and TSR are empty.
0 : THR is not empty.
1 : THR is empty. It indicates that the UART is ready to accept a new
0 : No break condition (default).
1 : The receiver received a break signal (RXD was ‘0’ for at least one
0 : No framing error (default).
1 : Framing error. It indicates that the received character did not have a
0 : No parity error (default).
1 : Parity error. It indicates that the receive character did not have the
0 : No overrun error (default).
1 : Overrun error. It indicates that the character in the RBR or RX FIFO
0 : No character in the RBR or RX FIFO.
1 : At least one character in the RBR or RX FIFO.
RX FIFO. This bit is cleared when there is no more error in any of
characters in the RX FIFO.
character for transmission. In addition, it uses the UART to gener-
ate an interrupt to the CPU when the THR empty interrupt enable
is set to ‘1’.
character frame time). In FIFO mode, only one character is loaded
into the RX FIFO.
valid stop bit.
correct even or odd parity, as selected by the LCR[4]
was not read by the CPU, thereby ignored the receiving character.