S25FL129P Meet Spansion Inc., S25FL129P Datasheet - Page 28

• Manufacturer Part Number: S25FL129P
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

9.3
28
Dual Output Read Mode (DOR)
The Dual Output Read instruction is similar to the FAST_READ instruction, except that the data is shifted out
2 bits at a time using 2 pins (SI/IO0 and SO/IO1) instead of 1 bit, at a maximum frequency of 80 MHz. The
Dual Output Read mode effectively doubles the data transfer rate compared to the FAST_READ instruction.
The host system must first select the device by driving CS# low. The Dual Output Read command is then
written to SI, followed by a 3-byte address (A23-A0) and a dummy byte. Each bit is latched on the rising edge
of SCK. Then the memory contents, at the address that is given, are shifted out two bits at a time through the
IO0 (SI) & IO1 (SO) pins at a frequency f
The Dual Output Read command sequence is shown in
address byte specified can start at any location of the memory array. The device automatically increments to
the next higher address after each byte of data is output. The entire memory array can therefore be read with
a single Dual Output Read command. When the highest address is reached, the address counter reverts to
00000h, allowing the read sequence to continue indefinitely.
It is important that the I/O pins be set to high-impedance prior to the falling edge of the first data out clock.
The Dual Output Read command is terminated by driving CS# high at any time during data output. The
device rejects any Dual Output Read command issued while it is executing a program, erase, or Write
Registers operation, and continues the operation uninterrupted.
SO/IO1
SI/IO0
CS#
SCK
Hi-Z
0
1
2
Instruction
3
4
Figure 9.3 Dual Output Read Instruction Sequence
5
6
D a t a
7
23
*
8
22 21
9 10
S25FL129P
C
S h e e t
Address
24 Bit
on the falling edge of SCK.
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
3
2
1
0
( P r e l i m i n a r y )
7
*
Figure 9.3
6
Dummy Byte
5
4
3
and
2
1
Table 9.1 on page
S25FL129P_00_04 November 2, 2009
0
7
*
6
4
5
SI Switches from Input to Output
Byte 1
3
2
0
1
6
7
*
5
Byte 2
4
25. The first
3
2
1
0
6
7
*MSB