S25FL129P Meet Spansion Inc., S25FL129P Datasheet - Page 39

• Manufacturer Part Number: S25FL129P
• Description: 128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
• Manufacturer: Meet Spansion Inc.

9.11
November 2, 2009 S25FL129P_00_04
Read Status Register (RDSR)
The Read Status Register (RDSR) command outputs the state of the Status Register bits.
the status register bits and their functions. The RDSR command may be written at any time, even while a
program, erase, or Write Registers operation is in progress. The host system should check the Write In
Progress (WIP) bit before sending a new command to the device if an operation is already in progress.
Figure 9.13
Register continuously until CS# is driven high. The maximum clock frequency for the RDSR command is
104 MHz.
The following describes the status and control bits of the Status Register.
Write In Progress (WIP) bit: Indicates whether the device is busy performing a Write Registers, program, or
erase operation. This bit is read-only, and is controlled internally by the device. If WIP is 1, one of these
operations is in progress; if WIP is 0, no such operation is in progress. This bit is a Read-only bit.
Write Enable Latch (WEL) bit: Determines whether the device will accept and execute a Write Registers,
program, or erase command. When set to 1, the device accepts these commands; when set to 0, the device
rejects the commands. This bit is set to 1 by writing the WREN command, and set to 0 by the WRDI
command, and is also automatically reset to 0 after the completion of a Write Registers, program, or erase
operation, and after a power down/power up sequence. WEL cannot be directly set by the WRR command.
Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against
any changes to the stored data. The Block Protection (BP2, BP1, BP0) bits are either volatile or non-volatile,
depending on the state of the non-volatile bit BPNV in the Configuration register. The Block Protection (BP2,
BP1, BP0) bits are written with the Write Registers (WRR) instruction. When one or more of the Block Protect
(BP2, BP1, BP0) bits is set to 1’s, the relevant memory area is protected against Page Program (PP),
SCK
CS#
SO
SI
Bit
7
6
5
4
3
2
1
0
Mode 3
Mode 0
Hi-Z
Status Register Bit
D a t a
shows the RDSR command sequence, which also shows that it is possible to read the Status
P_ERR
E_ERR
SRWD
WEL
BP2
BP1
BP0
WIP
0
1
Figure 9.13 Read Status Register (RDSR) Command Sequence
S h e e t
Command
2
3
4
Status Register Write Disable
Programming Error Occurred
5
Erase Error Occurred
Write Enable Latch
( P r e l i m i n a r y )
Write in Progress
Table 9.8 S25FL129P Status Register
Bit Function
Block Protect
6
7
MSB
S25FL129P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
8
Status Register Out
9
10
11
12
1 = Protects when W#/ACC is low
0 = No protection, even when W#/ACC is low
0 = No Error
1 = Error occurred
0 = No Error
1 = Error occurred
Protects selected Blocks from Program or Erase
1 = Device accepts Write Registers, program or erase commands
0 = Ignores Write Registers, program or erase commands
1 = Device Busy a Write Registers, program or erase operation is in
0 = Ready. Device is in standby mode and can accept commands.
13
progress
14
15
MSB
Status Register Out
Description
Table 9.8
shows
39