S25FL129P Meet Spansion Inc., S25FL129P Datasheet - Page 55

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S25FL129P

Manufacturer Part Number
S25FL129P
Description
128-mbit Cmos 3.0 Volt Flash Memory With 104-mhz Spi Serial Peripheral Interface Multi I/o Bus
Manufacturer
Meet Spansion Inc.
Datasheet

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11. Power-up and Power-down
November 2, 2009 S25FL129P_00_04
During power-up and power-down, certain conditions must be observed. CS# must follow the voltage applied
on V
(see
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.
No Read, Write Registers, program, or erase command should be sent to the device until V
V
the WEL bit is reset (0).
Each device in the host system should have the V
package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the V
When V
operations are disabled and the device does not respond to any commands. Note that data corruption may
result if a power-down occurs while a Write Registers, program, or erase operation is in progress.
CC
At power-up, V
At power-down, GND
CC
min., plus a delay of t
Figure 11.1
, and must not be driven low to select the device until V
CC
drops from the operating voltage to below the minimum V
D a t a
V
and
CC
CC
V
V
V
CC
CC
CC
V
(cut-off)
V
(min.) plus a period of t
(max)
cc
(min)
cc
(low)
Table 11.1 on page
S h e e t
(max)
(min)
V
V
CC
cc
PU
. At power-up, the device is in standby mode (not Deep Power-Down mode) and
Figure 11.2 Power-down and Voltage Drop
( P r e l i m i n a r y )
Figure 11.1 Power-Up Timing Diagram
S25FL129P
56):
PU
No Device Access Allowed
t
CC
PU
t
rail decoupled by a suitable capacitor close to the
PD
CC
reaches the allowable values as follows
Full Device Access
CC
t
threshold at power-down, all
PU
Device Access
Allowed
Time
time
CC
rises to the
CC
feed.
55

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