cs4297 Cirrus Logic, Inc., cs4297 Datasheet - Page 15

• Manufacturer Part Number: cs4297
• Description: Crystalclear Soundfusion Audio Codec 97 Logic
• Manufacturer: Cirrus Logic, Inc.

DS242F5
DIGITAL HARDWARE DESCRIPTION
AC’97 AC-Link
The AC-Link is the serial connection between the
AC’97 Controller and the CS4297. The interface
consists of 5 signal lines (2 data, 2 clocks, and 1 re-
set). The basic connections of the link are shown in
Figure 2. The signals will be explained in detail be-
low.
AC-Link Protocol
The CS4297 serial interface is designed according
to the AC’97 Specification to allow connection to
any AC’97 Controller. An AC-Link audio frame is
divided into 13 ‘slots’; 1 16-bit slot and 12 20-bit
slots. During each audio frame, data is passed bi-di-
rectionally between the CS4297 and the AC’97
Controller.
AC-Link Serial Data Output Frame
For the serial data output frame, the SYNC,
BIT_CLK, and SDATA_OUT signals are used. In
the serial data output frame, data is passed on the
SDATA_OUT pin FROM the AC’97 Controller
TO the CS4297. In Figure 3 and in the following
Frame Slot definitions, the position of each bit lo-
cation within the frame is noted. The first bit posi-
CS4297
CrystalClear™ SoundFusion™ Audio Codec ’97
SDATA_OUT
SDATA_IN
BIT_CLK
Bit Frame
Bit Frame
Position
Position
SYNC
81.4 nS
F255
F255
X
0
Codec
Ready
Valid
Frame
F0
F0
12.288 MHz
Slot 1
Valid
Slot 1
Valid
F1
F1
Slot 2
Valid
Slot 2
Valid
F2
F2
Tag Phase
Figure 3. AC-Link Input and Output Framing
Slot 0
F12
F12
X
0
F13
F13
0
X
F14
F14
X
0
F15
F15
X
0
(48 KHz)
F16
R/W
F16
20.8uS
0
Slot 1
tion in a new serial data frame is F0 and the last bit
position in the serial data frame is F255.
When SYNC goes active (high) and is sampled ac-
tive by the CS4297 (on the falling edge of
BIT_CLK), both devices are synchronized to a new
serial data frame. The data on the SDATA_OUT
pin at this clock edge is the final bit of the previous
serial data frame’s data. On the next rising edge of
BIT_CLK, the first bit of slot 0 is driven by the
AC’97 Controller on the SDATA_OUT pin. The
CS4297 latches in this data, as the first bit of the
frame, on the next falling edge of the BIT_CLK
clock signal.
F36
WD15
RD15
F36
F37
WD14
F37
RD14
Digital AC’97
Controller
Slot 2
Figure 2. AC-link Connections
Data Phase
LC17
F56
LP17
F56
F57
Slot 3
F57
LP16
LC16
SDATA_OUT
SDATA_IN
BIT_CLK
RESET#
SYNC
RP17
RC17
F76
F76
Slot 4
F97
F97
CS4297
X
0
Slots 5-12
F255
F255
0
X
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