cs4216 Cirrus Logic, Inc., cs4216 Datasheet - Page 23

• Manufacturer Part Number: cs4216
• Description: 16-bit Stereo Audio Codec Logic
• Manufacturer: Cirrus Logic, Inc.

per frame, Master sub-mode) reduces the DSP
interrupts in half since the control data is split
from the audio data. This circuit is comprised of
three independent sections which may individu-
ally be eliminated if not needed.
To load control data into the codec, three
HC597’s are utilized. These are both latches that
store the DSP-sent control data, and shift regis-
ters that shift the data into the codec. The codec
uses an inverted SSYNC signal to copy the
latches to the shift registers every frame. In this
diagram the DSP is assumed to have a data bus
bandwidth of at least 24 bits. If the DSP has less
than 24_bits, the three HC597s must be split into
two addresses. Since the HC597 internal latches
are copied to the shift registers, the latches con-
tinually hold the DSP-sent data; therefore, the
DS83F2
CS4216
MF1:CDOUT
SM4
MF3:CCLK
MF2:CDIN
MF4:CCS
MF5:INT
Figure 15. SM4 - Microcontroller Interface
SDOUT
SSYNC
MF6:F1
MF7:F2
MF8:F3
RESET
SCLK
SDIN
43
42
44
40
39
36
35
38
34
31
30
1
2
VD+
IRQ
General
Purpose
Port
Pins
Serial
Port
Controller
DSP
Micro-
DSP only needs to write data to the latches when
a change is desired.
The second section is comprised of an HC595
shift register and latch that is clocked by an in-
verted SCLK The data shifted into the HC595 is
transferred to the HC595’s latch by the SSYNC
signal. This HC595 captures the 8 bits prior to
the SSYNC signal (which is also MF4:CCS) go-
ing high. As shown in Figure 14, and assuming
the MF4:CCS (SSYNC) signal rises at bit 32,
the 8-bits prior to MF4:CCS rising are a copy of
all the important status bits. This allows one shift
register to capture all the important information.
The interrupt pin cannot reliably be used in this
configuration since the interrupt pin is cleared by
reading the control port which occurs asynchro-
CS4216
SM4
32 BPF
MF1:CDOUT
MF3:CCLK
MF2:CDIN
MF4:CCS
MF5:INT
Figure 16. SM4 - Minimum DSP Interface
SSYNC
MF6:F1
MF7:F2
MF8:F3
RESET
SDOUT
SCLK
SDIN
43
42
44
35
36
38
40
39
34
31
30
1
2
VD+
Hard Wired or
CS4216
DIP Switch
selectable
DSP
23