t81l0003a TM Technology Inc., t81l0003a Datasheet - Page 15

• Manufacturer Part Number: t81l0003a
• Description: Reduced I/o 8-bit Mcu
• Manufacturer: TM Technology Inc.

tm
! Refreshing the watchdog timer
The watchdog timer must be refreshed regularly to prevent reset request signal from becoming active. This requirement
imposes obligation on the programmer to issue two followed instructions. The first instruction sets wdt and the second one
swdt. The maximum allowed delay between settings of the wdt and swdt is 12 instruction cycles. While this period has
expired and swdt has not been set, wdt is automatically reset, otherwise the watchdog timer is reloaded with the content of
the wdtrel register and wdt is automatically reset. The procedure is as “Start procedure” before.
! Special Function Registers
a) Interrupt Enable 0 register (ien0)
The ien0 register (address : A8)
The ien0 bit functions
Bit
ien0.6
Note: other bits are not used to watchdog control
b) Interrupt Enable 1 register (ien1)
The ien1 register (Address : B8)
The ien1 bit functions
Bit
Ien1.6
Pay attention that when write ien1.6, it write the swdt bit, when read ien1.6, we will read out the wdts bit. Ie. Watch
dog timer status flag. Set by hardware when the watchdog timer was started.
TM Technology, Inc. reserves the right
to change products or specifications without notice.
MSB
MSB
eal
-
Symbol
wdt
Symbol
swdt
CH
TE
swdt
wdt
Function
Watchdog timer start refresh flag.
Set to active/refresh the watchdog timer. When directly set after setting wdt, a watchdog
timer refresh is performed. Bit swdt is reset by hardware 12 instruction cycles after it has
been set.
Function
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly before swdt is set to
prevent an unintentional refresh of the watchdog timer. The wdt is reset by hardware 12
instruction cycles after it has been set.
pt2
et2
es0
ps
pt1
et1
P. 15
px1
ex1
Publication Date: SEP. 2004
pt0
et0
T81L0003A
LSB
LSB
px0
ex0
Revision: C