t81l0003a TM Technology Inc., t81l0003a Datasheet - Page 7

• Manufacturer Part Number: t81l0003a
• Description: Reduced I/o 8-bit Mcu
• Manufacturer: TM Technology Inc.

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Program Status Word
Stack Pointer
While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07H after a reset. This causes the
stack to begin at locations 08H.
Data Pointer (DPTR)
16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Ports 1.0-1.7 & 3.0-3.4
port output pin to switch high. Writing a zero causes the port output pin to switch low. When used as an input, the external
state of a port pin will be held in the port SFR (i.e., if the external state of a pin is low, the corresponding port SFR bit will
contain a ‘0’; if it is high, the bit will contain a ‘1’).
TM Technology, Inc. reserves the right
to change products or specifications without notice.
The PSW register contains program status information as detailed in
BIT SYMBOL FUNCTION
PSW.7 CY Carry flag.
PSW.6 AC Auxilliary Carry flag. (For BCD operations.)
PSW.5 F0 Flag 0. (Available to the user for general purposes.)
PSW.4 RS1 Register bank select control bit 1.
PSW.3 RS0 Register bank select control bit 0.
PSW.2 OV Overflow flag.
PSW.1 — User-definable flag.
PSW.0 P Parity flag.
NOTE: The contents of (RS1, RS0) enable the working register banks as follows:
The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions.
The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a
All Ports are the SFR latches, respectively. Writing a one to a bit of a port SFR (P1 or P3) causes the corresponding
MSB
CY
Set/cleared by software to determine working register bank. (See Note.)
Set/cleared by software to determine working register bank. (See Note.)
Set/cleared by hardware each instruction cycle to indicate an odd/even number of “one” bits in the
Accumulator, i.e., even parity.
(0,0)— Bank 0 (00H–07H)
(0,1)— Bank 1 (08H–0fH)
(1,0)— Bank 2 (10H–17H)
(1,1)— Bank 3 (18H–1fH)
CH
TE
AC
F0
RS1
RS0
P. 7
OV
Publication Date: SEP. 2004
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T81L0003A
LSB
P
Revision: C