mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet
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mcf5274l Summary of contents
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... MCF5275 family. The MCF5275 family includes the MCF5275, MCF5275L, MCF5274 and MCF5274L microprocessors. The differences between these parts are summarized in document is written from the perspective of the MCF5275 and unless otherwise noted, the information applies also to the MCF5275L, MCF5274 and MCF5274L ...
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MCF5275 Family Configurations memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory controller. These devices are ideal for cost-sensitive applications requiring significant control processing for file management, connectivity, data buffering, and user interface, as well ...
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Module Debug BDM JTAG - IEEE 1149.1 Test Access Port Hardware Encryption Package 2 Block Diagram The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array (MAPBGA) package. Figure 1 shows a top-level ...
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Block Diagram FAST ETHERNET (To/From PADI) CONTROLLER (FEC0) FAST ETHERNET (To/From PADI) CONTROLLER (FEC1) (To/From 4 CH DMA PADI) DREQ[1:0] DACK[3:0] JTAG TAP JTAG_EN (To/From PADI PWM (To/From PADI) Watchdog Timer SKHA Full Speed RNGA (To/From PADI) MDHA ...
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Features This document contains information on a new product. Specifications and information herein are subject to change without notice. 3.1 Feature Overview • ColdFire version 2 variable-length RISC processor — Static operation — 32-bit address and data path on-chip ...
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Features — One FIFO RAM per endpoint (2-Kbyte total) — Dedicated 1-Kbyte descriptor RAM, accessible from the Slave bus — Remote wake-up • Hardware cryptography accelerator (optional) — Random number generator — DES/3DES/AES block cipher engine — MD5/SHA-1/HMAC accelerator • ...
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Low power mode support • Phase Locked Loop (PLL) — Reference crystal MHz — Low power modes supported — Separate CLKOUT and DDR_CLKOUT signals • Four Programmable Interrupt Timers (PITs) • Interrupt Controllers ...
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Features — Supports 16-bit wide memory devices — Supports Dual Data Rate (DDR) SDRAM. — Page mode support — Programmable refresh interval timer. — Sleep mode and self-refresh. — Supports 16-byte (4-beat, 4-byte) critical-word-first burst transfer. — Memory sizes from ...
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Supported operands include 16- and 32-bit signed and unsigned integers as well as signed fractional operands as well as a complete set of instructions to process these data types. The EMAC provides superb support ...
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Features 3.5 On-chip Memories The 64 Kbyte data RAM and the 16 Kbyte cache RAM for the processors are built using a RAM compiler. Both RAM blocks connect directly to the RAM controller via a standard single-port synchronous SRAM interface. ...
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Support for full-duplex operation (200Mbps throughput) with a minimum system clock of 50MHz • Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25MHz • IEEE 802.3 full duplex flow control • Programmable max frame ...
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Features 3.9 Cryptography Some of the MCF5275 family devices incorporate small, fast, and dedicated hardware accelerators for random number generation, message digest and hashing, and the DES, 3DES, and AES block cipher functions. This allows for the implementation of common ...
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Multiple-master operation • Software programmable for one of 64 different serial clock frequencies • Software selectable acknowledge bit • Interrupt driven, byte-by-byte data transfer • Arbitration lost interrupt with automatic mode switching from master to slave • Calling address ...
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Features Each of the four timer modules has four operating modes: • Capture mode • Output mode • Reference compare mode 3.14 Pulse Width Modulation (PWM) Module The Pulse Width Modulation (PWM) module generates a synchronous series of pulses having ...
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PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS. 3.17 Interrupt Controllers (INTC0/INTC1) There are two interrupt controllers which support 58 interrupt sources ...
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Features The key features of the EIM are summarized below: • Eight independent, user-programmable chip-select signals (CS[7:0]) that interface with various memory types and peripherals • Address masking for 64 Kbyte to 4 gigabyte memory block sizes • Programmable wait ...
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External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also software-readable status flags indicating the cause of the last reset. 3.22 General Purpose I/O Most peripheral I/O pins on MCF5275 devices are muxed with ...
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Signal Descriptions Table 2. Signal Information and Muxing (continued) Name A[20:0] D[31:16] BS[3: TEA R/W TSIZ1 TSIZ0 TS TIP CS[7:1] CS0 DDR_CLKOUT DDR_CLKOUT SD_CS[1:0] SD_SRAS SD_SCAS SD_WE SD_A10 SD_DQS[1:0] SD_CKE SD_VREF IRQ[7:5] IRQ[4] IRQ[3:2] IRQ1 MCF5275 Integrated Microprocessor ...
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Table 2. Signal Information and Muxing (continued) Name FEC0_MDIO FEC0_MDC FEC0_TXCLK FEC0_TXEN FEC0_TXD[0] FEC0_COL FEC0_RXCLK FEC0_RXDV FEC0_RXD[0] FEC0_CRS FEC0_TXD[3:1] FEC0_TXER FEC0_RXD[3:1] FEC0_RXER FEC1_MDIO FEC1_MDC FEC1_TXCLK FEC1_TXEN FEC1_TXD[0] FEC1_COL FEC1_RXCLK FEC1_RXDV FEC1_RXD[0] FEC1_CRS FEC1_TXD[3:1] FEC1_TXER FEC1_RXD[3:1] FEC1_RXER MCF5275 Integrated Microprocessor Family ...
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Signal Descriptions Table 2. Signal Information and Muxing (continued) Name I2C_SDA I2C_SCL DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads. Please refer to the following pins for muxing: PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for DACK1, TSIZ0 ...
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Table 2. Signal Information and Muxing (continued) Name USB_CLK USB_RN USB_RP USB_RXD USB_SUSP USB_TN USB_TP USB_TXEN DT3IN DT3OUT DT2IN DT2OUT DT1IN DT1OUT DT0IN DT0OUT DSCLK PSTCLK BKPT DSI DSO JTAG_EN DDATA[3:0] PST[3:0] TEST PLL_TEST MCF5275 Integrated Microprocessor Family Hardware Specification, ...
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Signal Descriptions Table 2. Signal Information and Muxing (continued) Name VDDPLL VSSPLL VDD VSS OVDD OVSS SD_VDD NOTES: 1 Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup enabled in GPIO mode with the ...
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Signal Name Abbreviation External Clock In EXTAL Crystal XTAL Clock Out CLKOUT 4.3 Mode Selection Table 5 describes signals used in mode selection. Signal Name Abbreviation Clock Mode Selection CLKMOD[1:0] Configure the clock mode after reset. Reset Configuration RCON 4.4 ...
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Signal Descriptions Table 6. External Memory Interface Signals (continued) Signal Name Abbreviation Byte Strobes BS[3:2] Output Enable OE Transfer Acknowledge TA Transfer Error TEA Acknowledge Read/Write R/W Transfer Size TSIZ[1:0] Transfer Start TS Transfer in Progress TIP Chip Selects CS[7:0] ...
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Signal Name Abbreviation SDRAM Clock Out DDR_CLKOUT This output signal reflects the internal system clock. SDRAM Inverted DDR_CLKOUT This output signal reflects the inverted internal system clock. Clock Out SDRAM Synchronous SD_SRAS Row Address Strobe SDRAM Synchronous SD_SCAS Column Address ...
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Signal Descriptions Table 9. Ethernet Module (FEC) Signals (continued) Signal Name Abbreviation Transmit Enable FECn_TXEN Transmit Data 0 FECn_TXD0 Collision FECn_COL Receive Clock FECn_RXCLK Receive Data Valid FECn_RXDV Receive Data 0 FECn_RXD0 Carrier Receive Sense FECn_CRS Transmit Data 1–3 FECn_TXD[3:1] ...
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Table 10. Queued Serial Peripheral Interface (QSPI) Signals Signal Name Abbreviation QSPI Syncrhonous QSPI_DOUT Serial Output QSPI Synchronous QSPI_DIN Serial Data Input QSPI Serial Clock QSPI_CLK Synchronous Peripheral QSPI_CS[1:0] Provide QSPI peripheral chip selects that can be programmed to be ...
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Signal Descriptions Signal Name Abbreviation Clear-to-Send UnCTS Request-to-Send UnRTS 4.11 USB Signals Table 13 describes the USB serial interface module signals. Signal Name Abbreviation USB Clock USB_CLK USB Speed USB_SPEED Applications which make use of low speed USB signalling must ...
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Signal Name Abbreviation USB Transmitted D+ USB_TP USB Transmit Enable USB_TXEN 4.12 DMA Timer Signals Table 14 describes the signals of the four DMA timer modules. Signal Name Abbreviation DMA Timer 0 Input DT0IN DMA Timer 0 Output DT0OUT DMA ...
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Signal Descriptions Signal Name Abbreviation PWM Output Channel 0 PWM0 PWM Output Channel 1 PWM1 PWM Output Channel 2 PWM2 PWM Output Channel 3 PWM3 4.14 Debug Support Signals These signals are used as the interface to the on-chip JTAG ...
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PST[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4.15 Test Signals Table 18 describes test signals. Signal Name Abbreviation Test TEST PLL Test PLL_TEST 4.16 Power and Ground Pins The pins ...
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Chip Configuration Signal Name Abbreviation PLL Analog Supply VDDPLL, VSSPLL Positive Supply VDDO Positive Supply VDD Ground VSS 5 Chip Configuration 5.1 Device Operating Options • Chip operating mode: — Master mode • Boot device/size: — External device boot – ...
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Chip Configuration Pins Chip Configuration Pin RCON Chip configuration enable D26, D17, D16 Select chip operating mode D19, D18 Select external boot device data port size D21 Select output pad drive strength CLKMOD1, Select clock mode CLKMOD0 D25, D24 ...
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Design Recommendations Inputs driven high or low as needed Figure 2. MCF5275 Recommended Reset Configuration Circuit 6 Design Recommendations 6.1 Layout • Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power and ...
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Decoupling • Place the decoupling capacitors as close to the pins as possible, but they can be outside the footprint of the package. • 0.1uF and 0.01uF at each supply input 6.4 Buffering • Use bus buffers on all ...
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Design Recommendations Table 21. Synchronous DRAM Signal Connections Signal SD_SRAS Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM SD_SRAS. Do not ...
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Table 22. Generic Address Multiplexing Scheme (continued) Address Pin Row Address Column Address The following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the MCF5275 to SDRAM. To ...
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Design Recommendations Table 26. MCF5275 to SDRAM Interface (8-Bit Port,12-Column Address Lines) MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row ...
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Table 31. MCF5275 to SDRAM Interface (16-Bit Port, 11-Column Address Lines) MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row Column ...
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Design Recommendations Table 36. MCF5275 to SDRAM Interface (32-Bit Port, 10-Column Address Lines) MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Pins Row ...
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Transmit clock Transmit enable Transmit data Transmit error Collision Carrier sense Receive clock Receive enable Receive data Receive error Management channel clock Management channel serial data The serial mode interface operates in what is generally referred to as AMD mode. ...
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Pinout 6.7.3 BDM Use the BDM interface as shown in the M5275EVB evaluation board user’s manual. The schematics for this board are accessible at the MCF5275 site by navigating from: http://e-www.motorola.com/ following the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx, MCF5275 and ...
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FEC1_ FEC1_ FEC1_ A VSS RXD1 RXDV CRS FEC1_ FEC1_ FEC1_ FEC1_ B RXD3 RXD2 RXD0 RXCLK FEC1_ FEC1_ FEC0_ FEC0_ C TXCLK RXER TXCLK RXER FEC1_ FEC1_ FEC0_ FEC0_ D TXER TXEN TXER TXEN FEC1_ ...
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... Pinout 7.2 196 MAPBGA Pinout Figure consolidated MCF5274L/75L pinout for the 196 MAPBGA package. by group and shows which signals are muxed and bonded on each of the device packages FEC0_ FEC0_ A NC U0RXD CRS MDIO FEC0_ FEC0_ FEC0_ FEC0_ B RXD2 RXD1 ...
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Mechanicals 8.1 Package Dimensions - 256 MAPBGA Figure 6 shows MCF5275 256 MAPBGA package dimensions LASER MARK FOR PIN A1 IDENTIFICATION IN THIS AREA E 0.20 15X ...
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Mechanicals X D Laser mark for pin 1 Y identification in this area E 0. 13X 3 b 196X View M-m 0. 0.10 Z Figure 6. 196 MAPBGA Package ...
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... Ordering Information Motorola Part Number MCF5274LVM133 MCF5274L RISC Microprocessor, 196 MAPBGA MCF5274LVM166 MCF5274L RISC Microprocessor, 196 MAPBGA MCF5274VM133 MCF5274 RISC Microprocessor, 256 MAPBGA MCF5274VM166 MCF5274 RISC Microprocessor, 256 MAPBGA MCF5275LCVM133 MCF5275L RISC Microprocessor, 196 MAPBGA MCF5275LCVM166 MCF5275L RISC Microprocessor, 196 MAPBGA ...
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Preliminary Electrical Characteristics Instantaneous Maximum Current Single pin limit (applies to all pins) Operating Temperature Range (Packaged) Storage Temperature Range NOTES: 1 Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings are stress ratings only, and functional ...
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Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. ...
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Preliminary Electrical Characteristics 2 A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing is performed per applicable device specification at room ...
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This parameter is characterized before qualification rather than 100% tested load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces require transmission line analysis to determine proper drive ...
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Preliminary Electrical Characteristics Characteristic Frequency un-LOCK Range Frequency LOCK Range 5, 6, 9,12, 13 CLKOUT Period Jitter, Peak-to-peak Jitter (Clock edge to clock edge) Long Term Jitter (Averaged over 2 ms interval) Frequency Modulation Range Limit (f Max must not ...
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Table 48. Processor Bus Input Timing Specifications Name B0 CLKOUT B1a Control input valid to CLKOUT high B1b BKPT valid to CLKOUT high B2a CLKOUT high to control inputs invalid B2b CLKOUT high to asynchronous control input BKPT invalid B4 ...
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Preliminary Electrical Characteristics * The timings are also valid for inputs sampled on the negative clock edge. CLKOUT (83MHz) Input Setup And Hold Input Rise Time Input Fall Time CLKOUT B4 Inputs Figure 7. General Input Timing Requirements 10.7 Processor ...
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Table 49. External Bus Output Timing Specifications (continued) Name Characteristic B9 CLKOUT high to address (A[23:0]) and control (TS, TSIZ[1:0], TIP, R/W) invalid B11 CLKOUT high to data output (D[31:16]) valid B12 CLKOUT high to data output (D[31:16]) invalid B13 ...
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Preliminary Electrical Characteristics S0 CLKOUT B6a CSn B8 A[23:0] TSIZ[1: TIP B8 B6c OE (H) R/W B6b BS[3:2] D[31:16] (H) TA TEA (H) Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing Figure 9 shows a bus cycle ...
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CLKOUT B6a CSn B8 A[23:0] TSIZ[1: TIP B6c OE R/W (H) B6b BS[3:2] D[31:16] TA TEA (H) Figure 9. SRAM Read Bus Cycle Terminated by TA Figure 10 shows an SRAM bus cycle terminated by TEA showing ...
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Preliminary Electrical Characteristics CLKOUT B6a CSn B8 A[23:0] TSIZ[1: TIP B6c OE R/W (H) B6b BS[3:2] D[31:16] TA (H) TEA Figure 10. SRAM Read Bus Cycle Terminated by TEA 10.8 DDR SDRAM AC Timing Characteristics The DDR ...
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Symbol V Clock output mid-point voltage MP V Clock output voltage level OUT V Clock output differential voltage (peak to peak swing Clock crossing point voltage IX NOTES nominally 2.5V. DD SDCLK SDCLK When ...
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Preliminary Electrical Characteristics 5 The first data beat will be valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The remaining data beats will be valid for each subsequent SD_DQS edge 6 Data input skew ...
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CLKOUT CLKOUT SD_CSn,SD_WE, SD_SRAS,SD_SCAS DD4 A[13:0] SD_DQS[3:2] D[31:16] SD_DQS[3:2] D[31:16] 10.9 General Purpose I/O Timing GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1, Interrupts and USB interfaces. When in GPIO mode the ...
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Preliminary Electrical Characteristics CLKOUT GPIO Outputs GPIO Inputs 10.10 Reset and Configuration Override Timing Table 53. Reset and Configuration Override Timing NUM Characteristic R1 RESET Input valid to CLKOUT High R2 CLKOUT High to RESET Input invalid 2 R3 RESET ...
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CLKOUT RESET RSTOUT 1 Configuration Overrides : (RCON, Override pins]) 1. Refer to the Coldfire Integration Module (CIM) section for more information. Figure 16. RESET and Configuration Override Timing 10.11 Fast Ethernet AC Timing Specifications MII signals use TTL signal ...
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Preliminary Electrical Characteristics FECn_RXCLK (input) FECn_RXD[3:0] (inputs) FECn_RXDV FECn_RXER Figure 17. MII Receive Signal Timing Diagram 10.11.2MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK) Table 55 lists MII transmit channel timings. The transmitter functions correctly minimum ...
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FECn_TXCLK (input) FECn_TXD[3:0] (outputs) FECn_TXEN FECn_TXER Figure 18. MII Transmit Signal Timing Diagram 10.11.3MII Async Inputs Signal Timing (FECn_CRS and FECn_COL) Table 56 lists MII asynchronous inputs signal timing. Table 56. MII asynchronous input signal timing Num M9 FECn_CRS, FECn_COL ...
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Preliminary Electrical Characteristics Table 57. MII serial management channel timings. Num M14 FECn_MDC pulse width high M15 FECn_MDC pulse width low Figure 20 shows MII serial management channel timings listed in FECn_MDC (output) FECn_MDIO (output) FECn_MDIO (input) Figure 20. MII ...
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Num US7 USB_CLK high to USB_TP, USB_TN, USB_SUSP valid US8 USB_CLK high to USB_TP, USB_TN, USB_SUSP invalid Figure 21 shows USB interface timings listed in USB_CLK USB Outputs USB Inputs Input Rise Time Input Fall Time 2 10. ...
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Preliminary Electrical Characteristics 2 Table 59 Input Timing Specifications between I2C_SCL and I2C_SDA Num I6 Clock high time I7 Data setup time I8 Start condition setup time (for repeated start condition only) I9 Stop condition setup time Table ...
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I2 SCL I1 SDA 10.13 DMA Timers Timing Specifications Table 61 lists timer module AC timings. Table 61. Timer Module AC Timing Specifications Name T1 T0IN / T1IN / T2IN / T3IN cycle time T2 T0IN / T1IN / T2IN ...
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Preliminary Electrical Characteristics QS1 QSPI_CS[3:0] QSPI_CLK QSPI_DOUT QS3 QSPI_DIN 10.15 JTAG and Boundary Scan Timing Num Characteristics J1 TCLK Frequency of Operation J2 TCLK Cycle Period J3 TCLK Clock Pulse Width J4 TCLK Rise and Fall Times J5 Boundary Scan ...
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TCLK (input) TCLK V Data Inputs Data Outputs Data Outputs Data Outputs MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Figure 24. Test Clock Input Timing ...
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Preliminary Electrical Characteristics TCLK V IL TDI TMS TDO TDO TDO TCLK TRST 10.16 Debug AC Timing Specifications Table 64 lists specifications for the debug AC timing parameters shown in Num D0 PSTCLK cycle time D1 PST, DDATA to CLKOUT ...
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Num D5 DSCLK cycle time D6 BKPT input data setup time to CLKOUT Rise D7 BKPT input data hold time to CLKOUT Rise D8 CLKOUT high to BKPT high Z NOTES: 1 DSCLK and DSI are synchronized internally ...
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Device/Family Documentation List 11 Device/Family Documentation List Motorola Document Number MCF5275EC/D MCF5275 RISC Microprocessor Hardware Specifications MCF5275RM/D MCF5275PB/D MCF5275FS CFPRODFACT/D The ColdFire Family of 32-Bit Microprocessors Family Overview and Technology Roadmap MCF5XXXWP MCF5XXXWP WHITE PAPER: Motorola ColdFire VL MAPBGAPP CFPRM/D ...
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THIS PAGE INTENTIONALLY LEFT BLANK MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Freescale Semiconductor Preliminary Document Revision History 75 ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2004. ...