mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 24

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

Signal Descriptions
4.5
Table 7
24
Byte Strobes
Output Enable
Transfer Acknowledge
Transfer Error
Acknowledge
Read/Write
Transfer Size
Transfer Start
Transfer in Progress
Chip Selects
describes signals that are used for DDR SDRAM accesses.
Signal Name
DDR SDRAM Controller Signals
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
BS[3:2]
OE
TA
TEA
R/W
TSIZ[1:0]
TS
TIP
CS[7:0]
Abbreviation
Table 6. External Memory Interface Signals (continued)
Define the flow of data on the data bus. During SRAM and peripheral
accesses, these output signals indicate that data is to be latched or
driven onto a byte of the data when driven low. The BS[3:2] signals are
asserted only to the memory bytes used during a read or write access.
BS3 controls access to the most significant byte lane of data, and BS2
controls access to the least significant byte lane of data.
The BS[3:2] signals are asserted during accesses to on-chip
peripherals but not to on-chip SRAM, or cache. During SDRAM
accesses, these signals act as the CAS[3:2] signals, which indicate a
byte transfers between SDRAM and the chip when driven high.
For SRAM or Flash devices, the BS[3:2] outputs should be connected
to individual byte strobe signals.
For SDRAM devices, the BS[3:2] should be connected to individual
SDRAM DQM signals. Note that most SDRAMs associate DQM1 with
the MSB, in which case BS3 should be connected to the SDRAM's
DQM1 input.
Indicates when an external device can drive data during external read
cycles.
Indicates that the external data transfer is complete. During a read
cycle, when the processor recognizes TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes TA, the bus cycle is terminated.
Indicates an error condition exists for the bus transfer. The bus cycle
is terminated and the CPU begins execution of the access error
exception.
Indicates the direction of the data transfer on the bus for SRAM (R/W)
and SDRAM (SD_WE) accesses. A logic 1 indicates a read from a
slave device and a logic 0 indicates a write to a slave device
When the device is in normal mode, dynamic bus sizing lets the
programmer change data bus width between 8, 16, and 32 bits for
each chip select. The initial width for the bootstrap program chip
select, CS0, is determined by the state of TSIZ[1:0]. The program
should select bus widths for the other chip selects before accessing
the associated memory space. These pins our output pins.
Bus control output signal indicating the start of a transfer.
Bus control output signal indicating bus transfer in progress.
These output signals select external devices for external bus
transactions. The CS[3:2] can also be configured to function as
SDRAM chip selects SD_CS[1:0].
Preliminary
Function
Freescale Semiconductor
I/O
O
O
O
O
O
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I
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