mcf5274l Freescale Semiconductor, Inc, mcf5274l Datasheet - Page 27

• Manufacturer Part Number: mcf5274l
• Description: Mcf5275 Integrated Microprocessor Family Hardware
• Manufacturer: Freescale Semiconductor, Inc

4.9
Table 11
4.10 UART Module Signals
The UART modules use the signals in this section for data. The baud rate clock inputs are not supported.
Freescale Semiconductor
QSPI Syncrhonous
Serial Output
QSPI Synchronous
Serial Data Input
QSPI Serial Clock
Synchronous Peripheral
Chip Selects
Transmit Serial Data
Output
Receive Serial Data
Input
Serial Clock
Serial Data
Signal Name
Signal Name
Signal Name
describes the I
I
2
C I/O SIGNALS
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Table 10. Queued Serial Peripheral Interface (QSPI) Signals
2
QSPI_DOUT
QSPI_DIN
QSPI_CLK
QSPI_CS[1:0] Provide QSPI peripheral chip selects that can be programmed to be
UnTXD
UnRXD
C serial interface module signals.
I2C_SCL
I2C_SDA
Abbreviation
Abbreviation
Abbreviation
Table 12. UART Module Signals
Open-drain clock signal for the for the I
by the I
the clock input when the I
Open-drain signal that serves as the data input/output for the I
interface.
Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK. Each byte is sent
msb first.
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK. Each byte is
written to RAM lsb first.
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable. The output frequency is programmed
according to the following formula, in which n can be any value
between 1 and 255:
active high or low. QSPI_CS1 can also be configured as SDRAM clock
enable signal SD_CKE.
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, lsb first, on this pin at the
falling edge of the serial clock source.
Receiver serial data inputs for the UART modules. Data received on
this pin is sampled on the rising edge of the serial clock source lsb
first. When the UART clock is stopped for power-down mode, any
transition on this pin restarts it.
Table 11. I
2
C module when the bus is in the master mode or it becomes
Preliminary
2
C I/O Signals
SPI_CLK = f
2
C is in the slave mode.
Function
Function
Function
sys
2
C interface. Either it is driven
/2 yn
Signal Descriptions
2
C
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
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