c15bc1 aptina, c15bc1 Datasheet - Page 11

• Manufacturer Part Number: c15bc1
• Description: Mt9d014 1/4-inch 2mp Cmos Digital Image Sensor
• Manufacturer: aptina

Two-Wire Serial Register Interface
Protocol
Start Condition
Slave Address/Data Direction Byte
Acknowledge Bit
No-Acknowledge Bit
PDF: 0526161444/Source: 6112702771
MT0D014_DS - Rev. J 5/10 EN
1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no) acknowledge bit
4. a message byte
5. a stop condition
The two-wire serial interface bus enables read/write access to control and status regis-
ters within the sensor. This interface is designed to be compatible with the SMIA 1.0 Part
2: CCP2 Specification camera control interface (CCI), which uses the electrical charac-
teristics and transfer protocols of the I
I
input only and therefore never drives it LOW.
Data transfers on the two-wire serial interface bus are performed by a sequence of
low-level protocol elements:
The bus is idle when both SCLK and S
a start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
A start condition is defined as a HIGH-to-LOW transition on S
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a “repeated start” or “restart” condition.
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. The
default slave addresses used by the MT9D014 are 0x20 (write address) and 0x21 (read
address) in accordance with the SMIA specification. Alternate slave addresses of 0x30
(write address) and 0x31 (read address) can be selected by enabling and asserting the
S
An alternate slave address can also be programmed through R0x31FC.
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases S
edge bit by driving S
LOW and must be stable while SCLK is HIGH.
The no-acknowledge bit is generated when the receiver does not drive S
during the SCLK clock period following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
2
ADDR
C specification allow the slave device to drive SCLK LOW; the sensor uses SCLK as an
signal through the GPI pad.
DATA
LOW. As for data transfers, S
11
MT9D014: 1/4-Inch 2Mp CMOS Digital Image Sensor
DATA
2
C specification. The protocols described in the
are HIGH. Control of the bus is initiated with
DATA
. The receiver indicates an acknowl-
Two-Wire Serial Register Interface
Aptina reserves the right to change products or specifications without notice.
DATA
can change when SCLK is
DATA
©2007 Aptina Imaging Corporation. All rights reserved.
while SCLK is HIGH.
DATA
LOW
Preliminary