c15bc1 aptina, c15bc1 Datasheet - Page 33

• Manufacturer Part Number: c15bc1
• Description: Mt9d014 1/4-inch 2mp Cmos Digital Image Sensor
• Manufacturer: aptina

Figure 13:
PDF: 0526161444/Source:6112702771
MT0D014_DS - Rev. J 5/10 EN
EXTCLK
External Input Clock
ext_clk_freq_mhz
MT9D014 SMIA Profile 1/2 Clocking Structure
Pre_pll_clk_div
2(1, 2, 3.....64)
Notes:
Pre PLL
Divider
pll_ip_clk_freq_mhz
The parameter limit register space contains registers that declare the minimum and
maximum allowable values for:
• The frequency allowable on each clock
• The divisors that are used to control each clock
The following factors determine what are valid values, or combinations of valid values,
for the divider/multiplier control registers:
• The minimum/maximum frequency limits for the associated clock must be met.
• The minimum/maximum value for the divider/multiplier must be met.
• The value of pll_multiplier should be a multiple of 2 for Data/Strobe signalling.
• The op_pix_clk must never run faster than the vt_pix_clk to ensure that the CCP2
• Given the maximum programmed line length, the minimum blanking time, the
PLL input clock frequency range, after the pre-PLL divider stage, is 2.0–11.5 MHz.
The usage of the output clocks is:
• vt_pix_clk is used by the sensor core to control the timing of the pixel array. The
1. The combinations vt_sys_clk_div = 1 and vt_pix_clk_div = (4,6,8,10) are also supported even though the
2. The pll_multiplier only accepts even values when ccp2_class is set to data/clock signalling. Odd values
3. The default value for vt_sys_clk_div is outside the range of legal values defined by the capability regis-
PLL Input Clock
output data stream is contiguous.
maximum image width, the available PLL divisor/multiplier values, and the require-
ment that the output line time (including the necessary blanking) must be output in a
time equal to or less than the time defined by line_length_pck, the valid combinations
of the clock divisors.
sensor core produces one 10-bit pixel each vt_pix_clk period. The line length
capability register does not advertise this.
will be rounded down to the first even number by setting LSB to “0.”
ters. This results in correct behavior for the cases listed in Note 1. The default setting is selected to
ensure profile 0 behavior as default with the highest possible frame rate.
80(16,18 .....256)
PLL_multiplier
Multiplier
PLL
pll_op_clk_freq_mhz
PLL Output Clock
33
MT9D014: 1/4-Inch 2Mp CMOS Digital Image Sensor
1(1,2,4,6.......32)
op_sys_clk_div
vt_sys_clk_div
op_sys _clk
vt _sys_clk
Divider
1 (2,4,6)
Divider
Video Timing System Clock
vt_sys_clk_freq_mhz
Aptina reserves the right to change products or specifications without notice.
op _pix _clk _div
vt_sys_clk_freq_mhz
10 (4, 5, 6......10) 1
vt_pix_clk_div
op _pix _clk
vt _ pix _clk
10( 8, 10)
Divider
Divider
©2007 Aptina Imaging Corporation. All rights reserved.
Preliminary
op_sys_clk
vt_pix_clk
op_pix_clk
Clocking