mcm63r836 Freescale Semiconductor, Inc, mcm63r836 Datasheet - Page 14

• Manufacturer Part Number: mcm63r836
• Description: 8m Late Write Hstl
• Manufacturer: Freescale Semiconductor, Inc

MCM63R836 MCM63R918
14
SLEEP MODE
power mode. The sleep mode pine is asynchronous and
active high. During normal operation, the ZZ pin is pulled low.
When ZZ is pulled high, the chip will enter sleep mode where
the device will meet lowest possible power conditions. The
sleep mode timing diagram shows the modes of operation:
Normal Operation, No Read/Write Allowed, and Sleep Mode.
Normal Operation
and t ZZR nanoseconds after recovering from sleep. Clock
(K) must also meet cycle high and low times during these
periods. Two cycles prior to sleep, initiation of either a read or
write operation is not allowed.
No Read/Write Allowed
recovery from sleep, the assertion of any write or read signal
OVERVIEW
RAM is designed to operate in a manner consistent with
IEEE Standard 1149.1–1990 (commonly referred to as
JTAG), but does not implement all of the functions required
for IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the RAMs critical speed path. Nevertheless,
the RAM supports the standard TAP controller architecture.
(The TAP controller is the state machine that controls the
TAPs operation) and can be expected to function in a manner
that does not conflict with the operation of devices with IEEE
NOTES:
Logic Input Logic High
Logic Input Logic Low
Logic Input Leakage Current
CMOS Output Logic Low
CMOS Output Logic High
TTL Output Logic Low
TTL Output Logic High
This device is equipped with an optional sleep or low
All inputs must meet setup and hold times prior to sleep
During the period of time just prior to sleep and during
The serial boundary scan test access port (TAP) on this
1. 0 V
2. I OL 1
3. |I OH 1|
4. I OL 2
5. |I OH 2|
V in
100 µA @ V OL = 0.2 V. Sampled, not 100% tested.
8 mA @ V OL = 0.4 V.
100 µA @ V DDQ – 0.2 V. Sampled, not 100% tested.
8 mA @ V OH = 2.4 V.
V DD for all logic input pins.
SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION
Parameter
(2.375 V
Freescale Semiconductor, Inc.
For More Information On This Product,
TAP DC OPERATING CHARACTERISTICS
V DD
Go to: www.freescale.com
3.6 V, 0 C
T A
70 C, Unless Otherwise Noted)
is not allowed. If a write or read operation occurs during
these periods, the memory array may be corrupted. Validity
of data out from the RAM can not be guaranteed immediately
after ZZ is asserted (prior to being in sleep). During sleep
mode recovery, the output impedance must be given
additional time above and beyond t ZZR in order to match
desired impedance (see explanation in output impedance
circuitry section).
Sleep Mode
nects its internal clock buffer. The external clock may contin-
ue to run without impacting the RAMs sleep current (I ZZ ). All
outputs will remain in a high–Z state while in sleep mode. All
inputs are allowed to toggle. The RAM will not be selected,
and will not perform any reads or writes.
1149.1 compliant TAPs. The TAP operates using conven-
tional JEDEC Standard 8–1B low voltage (3.3 V) TTL/CMOS
logic level signaling.
DISABLING THE TEST ACCESS PORT
disable the TAP controller without interfering with normal
operation of the device, TCK must be tied to V SS to preclude
mid–level inputs. TDI and TMS are designed so an undriven
input will produce a response identical to the application of a
logic 1, and may be left unconnected. But they may also be
tied to V DD through a 1 k resistor. TDO should be left uncon-
nected.
Symbol
V OH 1
V OH 2
V OL 1
V OL 2
V IH 1
V IL 1
The RAM automatically deselects itself. The RAM discon-
It is possible to use this device without utilizing the TAP. To
I lkg
V DD – 0.2
– 0.3
Min
1.2
2.4
—
—
—
V DD + 0.3
MOTOROLA FAST SRAM
Max
0.4
0.2
0.4
—
—
5
Unit
µA
V
V
V
V
V
V
Notes
1
2
3
4
5