ltc4268cdkd-1-trpbf Linear Technology Corporation, ltc4268cdkd-1-trpbf Datasheet - Page 29

• Manufacturer Part Number: ltc4268cdkd-1-trpbf
• Description: High Power Pd With Synchronous Noopto Flyback Controller
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
Combining this with the previous V
an expression for V
programming resistors and secondary resistances:
The effect of nonzero secondary output impedance is
discussed in further detail; see Load Compensation Theory.
The practical aspects of applying this equation for V
are found in the Applications Information.
Feedback Amplifi er Dynamic Theory
So far, this has been a pseudo-DC treatment of fl yback
feedback amplifi er operation. But the fl yback signal is a
pulse, not a DC level. Provision is made to turn on the
fl yback amplifi er only when the fl yback pulse is present
using the enable signal as shown in the timing diagram
(Figure 12b).
Minimum Output Switch On Time (t
The LTC4268-1 affects output voltage regulation via
fl yback pulse action. If the output switch is not turned on,
there is no fl yback pulse and output voltage information
is not available. This causes irregular loop response and
startup/latch-up problems. The solution is to require the
primary switch to be on for an absolute minimum time per
each oscillator cycle. To accomplish this the current limit
feedback is blanked each cycle for t
is less than that developed under these conditions, forced
continuous operation normally occurs. See Applications
Information for further details.
Enable Delay Time (ENDLY)
The fl yback pulse appears when the primary side switch
shuts off. However, it takes a fi nite time until the transformer
primary side voltage waveform represents the output
voltage. This is partly due to rise time on the primary
side MOSFET drain node but, more importantly, is due
to transformer leakage inductance. The latter causes a
voltage spike on the primary side, not directly related to
V
OUT
=
⎛
⎝ ⎜
R
1
R
+
2
R
2
•
V
OUT
FB
•
in terms of the internal reference,
N
SF
⎞
⎠ ⎟
−
I
SEC
ON(MIN)
FLBK
•
ON(MIN)
( (
ESR R
expression yields
. If the output load
+
)
DS ON
(
)
)
OUT
output voltage. Some time is also required for internal
settling of the feedback amplifi er circuitry. In order to
maintain immunity to these phenomena, a fi xed delay is
introduced between the switch turn-off command and the
enabling of the feedback amplifi er. This is termed “enable
delay.” In certain cases where the leakage spike is not
suffi ciently settled by the end of the enable delay period,
regulation error may result. See Applications Information
for further details.
Collapse Detect
Once the feedback amplifi er is enabled, some mechanism
is then required to disable it. This is accomplished by a
collapse detect comparator, which compares the fl yback
voltage (FB) to a fi xed reference, nominally 80% of V
When the fl yback waveform drops below this level, the
feedback amplifi er is disabled.
Minimum Enable Time
The feedback amplifi er, once enabled, stays on for a fi xed
minimum time period termed “minimum enable time.”
This prevents lockup, especially when the output voltage
is abnormally low; e.g., during start-up. The minimum
enable time period ensures that the V
“pump up” and increase the current mode trip point to
the level where the collapse detect system exhibits proper
operation. This time is set internally.
Effects of Variable Enable Period
The feedback amplifi er is enabled during only a portion of
the cycle time. This can vary from the fi xed minimum enable
time described to a maximum of roughly the “off” switch
time minus the enable delay time. Certain parameters of
feedback amp behavior are directly affected by the variable
enable period. These include effective transconductance
and V
Load Compensation Theory
The LTC4268-1 uses the flyback pulse to obtain
information about the isolated output voltage. An error
CMP
node slew rate.
LTC4268-1
CMP
node is able to
29
42681fa
FB
.