ltc4268cdkd-1-trpbf Linear Technology Corporation, ltc4268cdkd-1-trpbf Datasheet - Page 30

• Manufacturer Part Number: ltc4268cdkd-1-trpbf
• Description: High Power Pd With Synchronous Noopto Flyback Controller
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
source is caused by transformer secondary current fl ow
through the synchronous MOSFET R
nonzero impedances of the transformer secondary and
output capacitor. This was represented previously by the
expression “I
more useful to convert this expression to effective output
impedance. Because the secondary current only fl ows
during the off portion of the duty cycle (DC), the effective
output impedance equals the lumped secondary impedance
divided by off time DC.
Since the off time duty cycle is equal to 1 – DC then:
where:
LTC4268-1
30
R
DC = duty cycle
R
R
R1
R2
S(OUT)
DS(ON)
S OUT
COMP I
(
16
FB
LOAD
)
Q3
= effective supply output impedance
22
Figure 13. Load Compensation Diagram
and ESR are as defi ned previously
=
SEC
ESR R
R
CMP
Q1 Q2
• (ESR + R
− 1
+
DC
DS ON
A1
(
V
FB
+
–
DS(ON)
)
21
).” However, it is generally
C
R
CMP
CMPF
50k
DS(ON)
SENSE
V
PORTP
20
V
FLBK
+
and real life
MP
R
42681 F13
•
•
SENSE
T1
•
This impedance error may be judged acceptable in less
critical applications, or if the output load current remains
relatively constant. In these cases the external FB resistive
divider is adjusted to compensate for nominal expected
error. In more demanding applications, output impedance
error is minimized by the use of the load compensation
function. Figure 13 shows the block diagram of the load
compensation function. Switch current is converted to a
voltage by the external sense resistor, averaged and lowpass
fi ltered by the internal 50k resistor R
capacitor on C
external R
producing a current at the collector of Q3 that is subtracted
from the FB node. This effectively increases the voltage
required at the top of the R1/R2 feedback divider to achieve
equilibrium.
The average primary side switch current increases to
maintain output voltage regulation as output loading
increases. The increase in average current increases R
resistor current which affects a corresponding increase
in sensed output voltage, compensating for the IR drops.
Assuming relatively fi xed power supply effi ciency, Eff,
power balance gives:
Average primary side current is expressed in terms of
output current as follow:
So the effective change in V
P
V
where:
thus
OUT
OUT
I
K1=
Δ
IN
Δ
Δ
V
V
I I
:
= K I
OUT
= Eff • P
• I
OUT
OUT
V
CMP
OUT
V
IN
1•
OUT
= 1
= 1
•
K
OUT
Eff
CMP
= Eff • V
resistor by op amp A1 and transistor Q3
K
IN
•
•
. This voltage is impressed across the
R
R
R
SENSE
R
CMP
SENSE
CMP
IN
• I
•
•
IN
R N
OUT
R N
1
1
•
•
target is:
SF
SF
CMPF
and the external
42681fa
CMP