ltc6803g-3 Linear Technology Corporation, ltc6803g-3 Datasheet - Page 17

• Manufacturer Part Number: ltc6803g-3
• Description: Ltc6803-1/ltc6803-3 - Multicell Battery Stack Monitor
• Manufacturer: Linear Technology Corporation

OPERATION
Data Link Layer
Clock Phase And Polarity: The LTC6803 SPI compatible
interface is configured to operate in a system using CPHA
= 1 and CPOL = 1. Consequently, data on SDI must be
stable during the rising edge of SCKI.
Data Transfers: Every byte consists of 8 bits. Bytes are
transferred with the most significant bit (MSB) first. On a
write, the data value on SDI is latched into the device on
the rising edge of SCKI (Figure 3). Similarly, on a read, the
data value output on SDO is valid during the rising edge of
SCKI and transitions on the falling edge of SCKI (Figure 4).
CSBI must remain low for the entire duration of a com-
mand sequence, including between a command byte and
subsequent data. On a write command, data is latched in
on the rising edge of CSBI.
CSBI
SCKI
SDO
SDI
CSBI
SCKI
SDI
MSB (CMD) BIT 6 (CMD)
MSB (CMD) BIT 6 (CMD)
Figure 3. Transmission Format (Write)
Figure 4. Transmission Format (Read)
LSB (PEC)
LSB (PEC) MSB (DATA)
Network Layer
PEC Byte: The packet error code (PEC) byte is a cyclic
redundancy check (CRC) value calculated for all of the
bits in a register group in the order they are passed, using
the initial PEC value of 01000001 (0x41) and the following
characteristic polynomial:
To calculate the 8-bit PEC value, a simple procedure can
be established:
1. Initialize the PEC to 0100 0001.
2. For each bit DIN coming into the register group, set
3. Update the 8-bit PEC as PEC[7] = PEC[6],
4. Go back to step 2 until all data are shifted. The 8-bit
x
IN0 = DIN XOR PEC[7], then IN1=PEC[0] XOR IN0,
IN2 = PEC[1] XOR IN0.
PEC[6] = PEC[5],……PEC[3] = PEC[2], PEC[2] = IN2,
PEC[1] = IN1, PEC[0] = IN0.
result is the final PEC byte.
8
MSB (DATA)
+ x
2
+ x + 1
LTC6803-1/LTC6803-3
LSB (PEC)
LSB (PEC)
680313 F04
680313 F03
17
680313f