nt2gc72b89g0nl Nanya Techology, nt2gc72b89g0nl Datasheet - Page 26

• Manufacturer Part Number: nt2gc72b89g0nl
• Description: 2gb 256m X 72 / 4gb 512m X 72 / 8gb 1g X 72 Pc3-10600 / Pc3-12800 Registered Ddr3 Sdram Dimm
• Manufacturer: Nanya Techology

NT2GC72B89G0NL/NT2GC72C89G0NL
NT4GC72B4PG0NL/NT4GC72C4PG0NL/NT4GC72B8PG0NL/NT4GC72C8PG0NL
NT8GC72B4NG0NL/NT8GC72C4NG0NL
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-10600 / PC3-12800
Registered DDR3 SDRAM DIMM
AC Timing Specifications for DDR3 SDRAM Devices Used on Module (1333MHz)
REV 1.0
05/2011
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
Average Clock Period
Average high pulse width
Average low pulse width
Absolute Clock Period
Absolute clock HIGH pulse width
Absolute clock LOW pulse width
Clock Period Jitter
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
Cycle to Cycle Period Jitter during DLL locking period
Duty Cycle Jitter
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n = 13, 14 . . . 49, 50 cycles
Data Timing
DQS, DQS# to DQ skew, per group, per access
DQ output hold time from DQS, DQS#
DQ low-impedance time from CK, CK#
DQ high impedance time from CK, CK#
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels
Data setup time to DQS, DQS# referenced to Vih(ac) / Vil(ac) levels
Data hold time from DQS, DQS# referenced to Vih(dc) / Vil(dc) levels
DQ and DM Input pulse width for each input
Data Strobe Timing
DQS,DQS# differential READ Preamble
DQS, DQS# differential READ Postamble
DQS, DQS# differential output high time
DQS, DQS# differential output low time
DQS, DQS# differential WRITE Preamble
DQS, DQS# differential WRITE Postamble
DQS, DQS# rising edge output access time from rising CK, CK#
DQS and DQS# low-impedance time
(Referenced from RL - 1)
DQS and DQS# high-impedance time
(Referenced from RL + BL/2)
DQS, DQS# differential input low pulse width
DQS, DQS# differential input high pulse width
DQS, DQS# rising edge to CK, CK# rising edge
DQS, DQS# falling edge setup time to CK, CK# rising edge
DQS, DQS# falling edge hold time from CK, CK# rising edge
Command and Address Timing
Parameter
tCK (DLL_OFF)
tCK(avg)
tCH(avg)
tCL(avg)
tCK(abs)
tCH(abs)
tCL(abs)
JIT(per)
JIT(per, lck)
tJIT(cc)
JIT(cc, lck)
tJIT(duty)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
tERR(nper)
tDQSQ
tQH
tLZ(DQ)
tHZ(DQ)
tDS(base)
AC175
tDS(base)
AC150
tDH(base)
DC100
tDIPW
tRPRE
tRPST
tQSH
tQSL
tWPRE
tWPST
tDQSCK
tLZ(DQS)
tHZ(DQS)
tDQSL
tDQSH
tDQSS
tDSS
tDSH
Symbol
26
tERR(nper)max = (1 + 0.68ln(n)) * tJIT(per)max
tERR(nper)min = (1 + 0.68ln(n)) * tJIT(per)min
-0.25
Min.
0.47
0.47
0.43
0.43
-118
-140
-155
-168
-177
-186
-193
-200
-205
-210
-215
0.38
-500
-255
-500
0.45
0.45
160
140
400
-80
-70
0.9
0.3
0.4
0.4
0.9
0.3
0.2
0.2
30
65
8
-
-
-
-
-
Max.: tCK(avg)max + tJIT(per)max
Min.: tCK(avg)min + tJIT(per)min
Refer to "Standard Speed Bins)
NANYA reserves the right to change products and specifications without notice.
DDR3-1333
Note 19
Note 11
Max.
0.53
0.53
0.55
0.55
0.25
160
140
118
140
155
168
177
186
193
200
205
210
215
125
250
250
255
250
250
80
70
© NANYA TECHNOLOGY CORPORATION
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-
-
-
-
-
-
-
-
-
-
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ns
ps
tCK(avg)
tCK(avg)
ps
tCK(avg)
tCK(avg)
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tCK(avg)
ps
ps
ps
ps
ps
ps
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Units
Notes