nt2gc72b89g0nl Nanya Techology, nt2gc72b89g0nl Datasheet - Page 4

• Manufacturer Part Number: nt2gc72b89g0nl
• Description: 2gb 256m X 72 / 4gb 512m X 72 / 8gb 1g X 72 Pc3-10600 / Pc3-12800 Registered Ddr3 Sdram Dimm
• Manufacturer: Nanya Techology

NT2GC72B89G0NL/NT2GC72C89G0NL
NT4GC72B4PG0NL/NT4GC72C4PG0NL/NT4GC72B8PG0NL/NT4GC72C8PG0NL
NT8GC72B4NG0NL/NT8GC72C4NG0NL
2GB: 256M x 72 / 4GB: 512M x 72 / 8GB: 1G x 72
PC3-10600 / PC3-12800
Registered DDR3 SDRAM DIMM
Input/Output Functional Description
REV 1.0
05/2011
TDQS9 – TDQS17
 – 
DQS0 – DQS17
BA0, BA1, BA2
V

 – 
V
ODT0, ODT1
CKE0, CKE1
DQ0 – DQ63
DD
DM0 – DM8
CB0 – CB7
SA0 – SA2
REFDQ,
CK0, CK1
, 
Symbol
A0 – A9
,
 – 
A10/AP
A12/



Par_In
,
V
SDA
SCL
A11
A13

DDSPD,
V
REFCA
,

V
SS
Output
Supply
Supply
Output
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Polarity
Active
Active
Active
Active
Active
Cross
Cross
point
point
High
High
High
Low
Low
-
-
-
-
-
-
-
-
-
-
-
-
-
The system clock inputs. All address and command lines are sampled on the cross point of the
rising edge of CK and falling edge of . A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized to the input clock. However,
CK1 and  are terminated but not used on RDIMMs.
Activates the DDR3 SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh mode.
Enable the command decoders for the associated rank of SDRAM when low and disables
decoders when high. When decoders are disabled, new commands are ignored and previous
operations continue. Other combinations of these input signals perform unique functions,
including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing
internal control words in the register device(s). For modules with two registers,  and  operate
similarly to  and  for the second set of register outputs or register control words.
When sampled at the positive rising edge of CK and falling edge of , signals 
define the operation to be executed by the SDRAM.
Asserts on-die termination for DQ, DM, DQS, and  signals if enabled via the DDR3 SDRAM
mode register.
The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask
by allowing input data to be written if it is low but blocks the write operation if it is high. In Read
mode, DM lines have no effect.
The data strobes, associated with one data byte, sourced with data transfers. In Write mode, the
data strobe is sourced by the controller and is centered in the data window. In Read mode, the
data strobe is sourced by the DDR3 SDRAM and is sent at the leading edge of the data window.
 signals are complements, and timing is relative to the cross point of respective DQS and
. If the module is to be operated in single ended strobe mode, all  signals must be tied on
the system board to V
TDQS/ is applicable for x8 DRAMs only. When enabled via mode register A11=1 in MR1,
DRAM will enable the same termination resistance function on TDQS/ that is applied to
DQS/. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data
mask function  is not used. X4/x16 DRAMs must disable the TDQS function via mode
register A11=0 in MR1.
Selects which DDR3 SDRAM internal bank of four or eight is activated.
During a Bank Activate command cycle, defines the row address when sampled at the cross point
of the rising edge of CK and falling edge of . During a Read or Write command cycle, defines
the column address when sampled at the cross point of the rising edge of CK and falling edge of
. In addition to the column address, AP is used to invoke autoprecharge operation at the end of
the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BAn defines the
bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low, then
BA0-BAn are used to define which bank to precharge.
Data Input/Output pins.
Check bits are used for ECC.
Power supplies for core, I/O, Serial Presence Detect, Temp sensor, and ground for the module.
Reference voltage for SSTL15 inputs.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM and temp sensor.
A resistor must be connected from the SDA bus line to V
up.
This signal is used to clock data into and out of the SPD EEPROM and Temp sensor.
Address pins used to select the Serial Presence Detect and Temp sensor base address.
The  pin is reserved for use to flag critical module temperature.
This signal resets the DDR3 SDRAM.
Parity bit for the Address and Control bus.
Parity error detected on the Address and Control bus. A resistor may be connected from bus line
to V
DD
on the system planar to act as a pull up.
SS
and DDR3 SDRAM mode registers programmed appropriately.
4
NANYA reserves the right to change products and specifications without notice.
Function
DDSPD
on the system planar to act as a pull
© NANYA TECHNOLOGY CORPORATION
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