tld4012 Tripath Technology Inc., tld4012 Datasheet - Page 6

• Manufacturer Part Number: tld4012
• Description: Adsl Line Driver Using Tripath Digital Power Processing Dpp ?
• Manufacturer: Tripath Technology Inc.

P I N D E S C R I P T I O N
P I N
6
EP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
Exposed pad
FORC_BIAS
P I N N A M E
AUTO_CLR
TH_FAULT
RESETB
LOPWR
EN_AC
FAULT
VDD15
VSS15
OUTN
OUTP
VDD5
VSS5
GND
GND
GND
R
FBN
FBP
INN
INP
NC
NC
NC
NC
NC
NC
NC
G0
G1
G2
G3
EXT
Analog output
Analog output
Power supply
Power supply
Power supply
Power supply
Digital output
Analog input
Analog input
Analog input
Analog input
Analog input
Analog input
(open drain)
Digital input
Digital input
Digital input
Digital input
Digital input
No Connect
Digital input
Digital input
No Connect
No Connect
No Connect
No Connect
No Connect
Digital input
No Connect
FUNCTION
Digital input
Substrate
Ground
Ground
Ground
PIN
Device Ground
Positive terminal of differential input
Device Ground
Negative 5V supply voltage
Negative terminal of differential output
Negative 15V supply voltage
Positive 15V supply voltage
Positive terminal of differential output
Positive 5V supply voltage
Device Ground
A logic high enables the input common-mode feedback loop,
and input bias current cancellation circuit
Negative terminal of differential input
Least Significant Bit of programmable gain select
Second Least Significant Bit of programmable gain select
Third Least Significant Bit of programmable gain select
Most Significant Bit of programmable gain select
A logic level high indicates that the device has an output short
circuit or that a thermal overload has occurred
When set to a logic high, the device forces the bias on
regardless of fault conditions Intended for test only
When set to a logic high, the device simulates a thermal fault.
Intended for test only
When AUTO_CLR is set to a logic low, a logic low pulse on
RESETB clears the internal Fault latch; otherwise, connect
RESETB to VDD5; Logic low puts device in disabled mode
When set to logic high, the device goes into low-power mode
Sets over-current limit
Feedback path for synthesized output impedance
Feedback path for synthesized output impedance
A logic high forces an immediate reset of the fault latch when
RESETB is a logic high. A logic low requires that the RESETB
pin be pulsed low to reset the fault latch
Exposed pad at underside of device; must be connected to
VSS15. Internally connected to the substrate.
PIN DESCRIPTION
T r i p a t h T e c h n o l o g y , I n c . - T e c h n i c a l I n f o r m a t i o n
TLD4012 – JB/Rev. 2.0a/05.02