sg2567rdr212452ia ETC-unknow, sg2567rdr212452ia Datasheet
sg2567rdr212452ia
Related parts for sg2567rdr212452ia
sg2567rdr212452ia Summary of contents
Page 1
... SG2567RDR212452HC 256Mx72 (2GB), DDR2, 240-pin DIMM, Registered, ECC, Parity, 128Mx4 Based, PC2-5300, DDR2-667-555, 30.00mm, 22Ω DQ termination, Green Module (RoHS Compliant). SG2567RDR212452IA 256Mx72 (2GB), DDR2, 240-pin DIMM, Registered, ECC, Parity, 128Mx4 Based, PC2-5300, DDR2-667-555, 30.00mm, 22Ω DQ termination, Green Module (RoHS Compliant). SG2567RDR212452IB ...
Page 2
... July 31, 2007 Added SG2567RDR212452SE to the Ordering Information on page 1. • February 2, 2007 Added SG2567RDR212452ES, SG2567RDR212452HC, SG2567RDR212452IA & SG2567RDR212452NB to the Ordering Information on page 1. • June 2, 2006 Datasheet released. Corporate Headquarters Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • ...
Page 3
DDR2 SDRAM Module - 128Mx4 Based 240-pin DIMM, Registered, ECC, Parity Features • Standard : JEDEC • Configuration : ECC • Cycle Time : 3.0ns • CAS# Latency (CL) : 4.0, 5.0 • Posted CAS#/Additive Latency (AL) : ...
Page 4
DDR2 240-pin DIMM Pin List (Contd.) Pin Pin Pin Pin Pin No. Name No. Name No. 21 DQ10 DDQ 22 DQ11 52 CKE0 DQ16 54 BA2 (NC) 84 ...
Page 5
Pin Description Table (Contd.) Symbol Type Polarity A0~A9, Input - A10/AP, A11~A13 DQ0~DQ63 Input/ - CB0~CB7 Output DQS0~DQS17 Input/ Positive Output Edge DQS0#~DQS17# Input/ Negative Output Edge SA0~SA2 Input - SDA Input/ - Output SCL Input - RESET# Input Active ...
Page 6
Block Diagram RCS0# RCS1# RCKE0 RCKE1 RODT0 RODT1 DQS0 DQS S# CKE ODT DQS0# DQS# DQ0 I DQ1 I/O 1 DQ2 I/O 2 DQ3 I/O 3 DQS1 DQS S# CKE ODT DQS1# DQS# DQ8 I DQ9 ...
Page 7
REG1~REG4 R 22Ω E CS0# RCS0 (U2~U19) CS1# G RCS1 (U20~U37) A0~A13 I RA0~RA13 to all devices (U2~U37) S BA0~BA1 RBA0~RBA1 to all devices (U2~U37) T RAS# RRAS# to all devices (U2~U37) E CAS# ...
Page 8
Physical Dimensions 240-pin DIMM Module 1 5.175 5.00 FULL 1.50±0.10 2.50 Detail A (All dimensions are in millimeters with ±0.15mm tolerance unless specified otherwise.) Corporate Headquarters Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 ...
Page 9
Serial Presence Detect Table (SG2567RDR212452ES/HC/IA/IB/NA/NB/SC/SE) Byte No. Byte Description bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type row address on this ...
Page 10
Serial Presence Detect Table (Contd.) Byte No. Byte Description 27 Minimum row precharge time (=tRP) 28 Minimum row active to row active delay (=tRRD) 29 Minimum RAS to CAS delay (=tRCD) 30 Minimum activate precharge time (=tRAS) 31 Module row ...
Page 11
Serial Presence Detect Table (Contd.) Byte No. Byte Description 73~90 Manufacturer part # 91 Manufacturer revision code 92 ........Manufacturer revision code 93 Manufacturing data (Year) 94 Manufacturing data (Week) 95~98 Assembly serial # 99~125 Manufacturer specific data 126~255 Unused storage ...
Page 12
Mode Register Table Definition The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, t ous applications. The default value of the mode ...
Page 13
Extended Mode Register Table Definition The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, ODT (R (OCD), DQS# enable/disable, RDQS/RDQS# enable/disable, and OUTPUT enable/disable. The extended mode ...
Page 14
Extended Mode Register Table BA2 BA1 BA0 A15 A14 A13 E18 E17 E16 E15 E14 E13 EMR E17 E16 MRS mode 0 0 MRS 0 1 EMRS ( EMRS (2) 1 ...
Page 15
Commands The following Truth Tables provide a general reference of available commands. For a more detailed description please refer to the device data sheets. Truth Table - Commands Function Previous cycle (Extended) Mode Register Set H Refresh H Self Refresh ...
Page 16
Absolute Maximum Ratings Parameter Voltage on V relative Voltage on V relative to V DDQ SS Voltage on any pin relative to V Voltage on V relative to V DDSPD Operating Temperature (Ambient) Operating Temperature (Case) ...
Page 17
Capacitance (V = 1.8V±0.1V +25°C) DD Case Parameter Input Capacitance (CKn, CKn#) Input Capacitance delta (CKn, CKn#) Input Capacitance (all other input-only pins) Input Capacitance delta (all other input-only pins) Input/Output Capacitance (DQ, DM, DQS, DQS#, CB) Input/Output ...
Page 18
ODT DC Electrical Characteristics Parameter R effective impedence value for 75Ω TT setting EMR (A6, A2 effective impedence value for 150Ω TT setting EMR (A6, A2 effective impedence value for 50Ω TT ...
Page 19
OCD Default Output Characteristics (V = 1.8V±0.1V 0V Parameter Output Impedance Pull-up and Pull-down mismatch Output Slew Rate Output Step Size for Calibration Notes: 1. Absolute specifications: 0°C ≤ Impedance measurement condition for ...
Page 20
IDD Specification Parameters and Test Conditions (V = 1.8V±0.1V 0V Symbol Parameter IDD0 Operating one bank active–precharge current CKE and CS# are HIGH between valid commands; Address bus inputs are RASmin(IDD) SWITCHING; ...
Page 21
IDD Specification Parameters and Test Conditions (Contd.) Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is specified by AC Parametric Test Condition. 3. IDD parameters are specified with ODT disabled. 4. Data ...
Page 22
Parameter Clock cycle time Clock high-level width Clock low-level width Clock half period DQ output access time from CK/CK# Data-out high-impedence window from CK/CK# Data-out low-impedence window from CK/CK# DQ & DM input setup time relative to DQS DQ & ...
Page 23
Device AC Operating Conditions (Contd.) Parameter ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto ...
Page 24
Notes: 1. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as ...
Page 25
Disclaimer: No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of SMART Modular Technologies, Inc. (“SMART”). The ...