sg2567rdr212452ia ETC-unknow, sg2567rdr212452ia Datasheet - Page 15

• Manufacturer Part Number: sg2567rdr212452ia
• Description: Dram Module Ddr2 Sdram 2gbyte 240rdimm
• Manufacturer: ETC-unknow

Commands
The following Truth Tables provide a general reference of available commands. For a more detailed description please refer to
the device data sheets.
Truth Table - Commands
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
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(Extended) Mode Register Set
Refresh
Self Refresh Entry
Self Refresh Exit
Single Bank Precharge
Precharge All Banks
Bank Activate
Write
Write with Auto-Precharge
Read
Read with Auto-Precharge
No Operation
Device Deselect
Power Down Entry
Power Down Exit
All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock.
Bank addresses BA0, BA1, BA2 (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
Burst reads or writes at BL=4 cannot be terminated or interrupted.
The Power Down Mode does not perform any refresh operations. The duration of power down is therefore limited by the refresh require-
The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
“X” means “H or L (but a defined logic level)”.
Self Refresh Exit is asynchronous.
An = A12 for 256Mb, A13 for 512Mb & 1 Gb, A14 for 2Gb.
BAn = BA1 for up to 512Mb , BA2 for 1 Gb & 2Gb.
ments.
Function
Previous
cycle
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CKE
Current
cycle
H
H
H
H
H
H
H
H
H
H
X
X
H
L
L
CS#
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS#
H
H
H
H
H
H
H
H
L
L
L
X
L
L
L
X
X
X
CAS#
H
H
H
H
H
H
H
L
L
L
X
L
L
L
L
X
X
X
WE#
H
H
H
H
H
H
H
H
H
L
X
L
L
L
L
X
X
X
SG2567RDR212452UU
BA0~
BAn
BA
BA
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
9
An
Column
Column
Column
Column
8
X
X
X
X
X
X
X
X
X
~A11
Row Address
OP Code
A10
X
X
X
H
H
H
X
X
X
X
L
L
L
July 31, 2007
Column
Column
Column
Column
A9~A0
X
X
X
X
X
X
X
X
X
1, 2
1, 2, 3
1, 2, 3
Notes
1
1
1, 7
1, 2
1
1, 2
1, 2, 3
1, 2, 3
1
1
1, 4
1, 4
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