sg2567rdr212452ia ETC-unknow, sg2567rdr212452ia Datasheet - Page 12

• Manufacturer Part Number: sg2567rdr212452ia
• Description: Dram Module Ddr2 Sdram 2gbyte 240rdimm
• Manufacturer: ETC-unknow

Mode Register Table Definition
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency, burst
length, burst sequence, test mode, DLL reset, t
ous applications. The default value of the mode register is not defined, therefore the mode register must be written after power-
up for proper operation. The mode register is written by asserting low on CS#, RAS#, CAS#, WE#, BA0 and BA1, while control-
ling the state of address pins A0~A15. The DDR2 SDRAM should be in all bank precharge with CKE already high prior to writing
into the mode register. The mode register set command cycle time (t
mode register. The mode register contents can be changed using the same command and clock cycle requirements during nor-
mal operation as long as all banks are in the precharge state. The mode register is divided into various fields depending on
functionality. Burst length is defined by A0~A2 with options of 4 and 8 bit burst lengths. The burst length decodes are compatible
with DDR SDRAM. Burst address sequence type is defined by A3, CAS latency is defined by A4~A6. The DDR2 doesn’t sup-
port half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must be set to low for normal MRS opera-
tion. Write recovery time t
Notes:
1.
2.
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BA2
M18
M17
0
0
0
1
1
1
BA2 and A14~A15 are reserved for future use and must be programmed to 0 when setting the mode register.
WR min is determinedby t
(in ns) and rounding up to the next integer. The mode register must be programmed to this value.
M17
BA1
M16
0
1
0
1
M12
MR
0
1
BA0
M16
EMRS (2): Reserved
EMRS (3): Reserved
Active power
down exit time
Fast exit (t
Slow exit (t
MRS mode
EMRS (1)
M15
A15
0
MRS
1
WR
M8
XARD
M14
0
1
A14
XARDS
CK
0
1
is defined by A9~A11.
max and WR max is determined by t
)
DLL Reset
No
Yes
M13
A13
)
0
Write recovery for autoprecharge
M12
A12
M11
PD
0
0
0
0
1
1
1
1
M11
A11
WR
M10
0
0
1
1
0
0
1
1
and various vendor specific options to make DDR2 SDRAM useful for vari-
WR
M10
A10
M9
0
1
0
1
0
1
0
1
M7
0
1
M9
A9
Mode
Normal
Test
WR (cycles)
CK
DLL
M8
A8
Reserved
Reserved
Reserved
min. WR in clock cycles is calculated by dividing t
2
3
4
5
6
MRD
TM
M7
A7
) is required to complete the write operation to the
2
M6
A6
CAS Latency
SG2567RDR212452UU
M5
A5
M3
0
1
M4
A4
Burst Type
Sequential
Interleave
M3
BT
A3
CAS Latency
M6
0
0
0
0
1
1
1
1
M2
A2
Burst Length
M5
0
0
1
1
0
0
1
1
M1
Burst Length
A1
M2
0
0
M4
M0
A0
0
1
0
1
0
1
0
1
July 31, 2007
M1
WR
1
1
Address Field
Mode Register
2.0 (optional)
3.0 (optional)
6.0 (optional)
(in ns) by t
Reserved
Reserved
Reserved
Latency
M0
0
1
4.0
5.0
BL
12
CK
4
8