ics9248-102 Integrated Device Technology, ics9248-102 Datasheet

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ics9248-102

Manufacturer Part Number
ics9248-102
Description
Motherboard Single Chip Clock Solution For Pentium Ii/iii And K6 Processors, Using Sis540/sis630 Style Chipset
Manufacturer
Integrated Device Technology
Datasheet
Frequency Generator & Integrated Buffers for Celeron & PII/III™ & K6
Recommended Application:
Motherboard Single chip clock solution for Pentium II/III and
K6 processors, using SIS540/SIS630 style chipset
Output Features:
Features:
Skew Specifications:
Block Diagram
0317A—03/20/02
3- CPUs @ 2.5/3.3V, up to 166MHz.
14 - SDRAM @ 3.3V, up to166MHz.
7- PCI @3.3V,
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I
(Default is 24MHz).
2- REF @3.3V, 14.318MHz.
Up to 166MHz frequency support
Support FS0-FS3 trapping status bit for I
Support power management: CPU, PCI, SDRAM stop
and Power down Mode from I
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
FS0, FS1, FS3 must have a internal 120K pull-Down
to GND.
Uses external 14.318MHz crystal
CPU - CPU: < 175ps
SDRAM - SDRAM < 250ps
PCI - PCI: < 500ps
CPU - SDRAM: < 500ps
CPU (early) - PCI: 1-4ns (typ. 2ns)
Integrated
Circuit
Systems, Inc.
2
C programming.
2
C
2
C read back.
Functionality
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
3
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
1 These are double strength.
* These inputs have a 120K pull down to GND.
F
0
0
0
0
0
0
0
0
S
1
1
1
1
1
1
1
1
1
48-Pin 300mil SSOP
Pin Configuration
F
S
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
(
1
6
6
6
8
9
9
9
C
M
6
0
5
3
0
0
3
6
1
6
6
6
3
0
5
5
0
0
3
0
0
3
6
6
P
2
H
8 .
8 .
8 .
3 .
0 .
0 .
0 .
2 .
3 .
6 .
2 .
2 .
6 .
0 .
0 .
0 .
U
) z
2
2
2
3
0
0
0
3
4
4
3
3
4
0
1
0
S
1
1
1
1
1
1
1
1
1
1
1
1
(
6
8
9
9
D
M
6
ICS9248-102
0
0
0
0
3
3
5
3
2
1
1
6
3
0
5
R
0
0
0
0
3
3
0
3
6
2
1
6
H
7 .
3 .
0 .
0 .
2 .
0 .
0 .
0 .
0 .
3 .
0 .
1 .
6 .
0 .
0 .
5 .
A
) z
5
0
0
0
0
0
0
0
0
3
0
0
7
0
0
M
0
P
(
C
3
3
2
3
3
3
3
2
2
3
3
3
3
3
3
3
M
7
7
7
0
1
1
7
7
7
3
3
3
3
3
3
3
C I
H
5 .
5 .
7 .
0 .
6 .
6 .
3 .
6 .
6 .
4 .
4 .
4 .
4 .
4 .
4 .
4 .
) z
L
7
7
9
9
8
0
7
7
4
1
1
1
1
1
1
1
K
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(
R
M
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
3 .
E
H
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
F
) z
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

Related parts for ics9248-102

ics9248-102 Summary of contents

Page 1

... ICS9248-102 Pin Configuration 48-Pin 300mil SSOP ...

Page 2

... ICS9248-102 General Description The ICS9248-102 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding ...

Page 3

... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The 3 ICS9248-102 2 C programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK Byte Count ...

Page 4

... ICS9248-102 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...

Page 5

... Note: Don’t write into this register, writing into this 5 ICS9248-102 ...

Page 6

... ICS9248-102 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 102 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function ...

Page 7

... Settling Time Clk Stabilization T From = 3 target Freq 1 STAB Skew1 TCPU-PCI Guaranteed by design, not 100% tested in production. = 3.3 V +/-5% (unless otherwise stated) CONDITIONS = 3 From 1st crossing to 1% target Freq. 7 ICS9248-102 +0 MIN TYP MAX -0.3 0.8 SS 180 ...

Page 8

... ICS9248-102 Electrical Characteristics - CPU 70C 3.3V +/-5 PARAMETER SYMBOL Output Impedance R DSP2A Output Impedance R DSN2A Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I OL2B Rise Time tr 2A Fall Time t f2A Duty Cycle d t2A ...

Page 9

... *(0. - 2 0 ICS9248-102 TYP MAX UNITS Ω 55 Ω 0 1.925 74.5 250 ps 150 ps 150 500 ps TYP MAX UNITS Ω 20 Ω ...

Page 10

... ICS9248-102 TOP VIEW A 2 SEE DETAIL “A” ° 0 Ordering Information ICS9248yF-102-T Example: ICS XXXX PPP - T ...

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